@misc{WenBaroniPerezetal., author = {Wen, Jianan and Baroni, Andrea and Perez, Eduardo and Uhlmann, Max and Fritscher, Markus and KrishneGowda, Karthik and Ulbricht, Markus and Wenger, Christian and Krstic, Milos}, title = {Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator}, series = {2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}, journal = {2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}, publisher = {IEEE}, isbn = {978-3-9819263-8-5}, issn = {1558-1101}, doi = {10.23919/DATE58400.2024.10546709}, pages = {1 -- 6}, abstract = {The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 \% and 18 \%, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83\% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero.}, language = {en} } @misc{FritscherSinghRizzietal., author = {Fritscher, Markus and Singh, Simranjeet and Rizzi, Tommaso and Baroni, Andrea and Reiser, Daniel and Mallah, Maen and Hartmann, David and Bende, Ankit and Kempen, Tim and Uhlmann, Max and Kahmen, Gerhard and Fey, Dietmar and Rana, Vikas and Menzel, Stephan and Reichenbach, Marc and Krstic, Milos and Merchant, Farhad and Wenger, Christian}, title = {A flexible and fast digital twin for RRAM systems applied for training resilient neural networks}, series = {Scientific Reports}, volume = {14}, journal = {Scientific Reports}, number = {1}, publisher = {Springer Science and Business Media LLC}, issn = {2045-2322}, doi = {10.1038/s41598-024-73439-z}, pages = {13}, abstract = {Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the "ideal memristor" which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a "push button" modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).}, language = {en} } @misc{FritscherWengerKrstic, author = {Fritscher, Markus and Wenger, Christian and Krstic, Milos}, title = {From device to application - integrating RRAM Accelerator Blocks into large AI systems}, series = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, journal = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, publisher = {IEEE}, isbn = {979-8-3503-5411-9}, issn = {2159-3477}, doi = {10.1109/ISVLSI61997.2024.00111}, pages = {592 -- 592}, abstract = {This work provides an introduction to design methodologies for RRAM-based systems. We illustrate the impact of device variation on the performance of neural networks and propose a circuit-level integration approach for RRAM-based compute blocks. Moreover, we demonstrate a possible architectural integration by incorporating RRAM-based VMM blocks fabricated in a 130 nm CMOS process into a RISC-V.}, language = {en} } @misc{FritscherUhlmannOstrovskyyetal., author = {Fritscher, Markus and Uhlmann, Max and Ostrovskyy, Philip and Reiser, Daniel and Chen, Junchao and Schubert, Andreas and Schulze, Carsten and Kahmen, Gerhard and Fey, Dietmar and Reichenbach, Marc and Krstic, Milos and Wenger, Christian}, title = {Area-efficient digital design using RRAM-CMOS standard cells}, series = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, volume = {18}, journal = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, publisher = {IEEE}, isbn = {979-8-3503-5411-9}, issn = {2159-3477}, doi = {10.1109/ISVLSI61997.2024.00026}, pages = {81 -- 87}, abstract = {Extending the scalability of digital integrated circuits through novel device concepts is an attractive option. Among these concepts, resistive random access memory (RRAM) devices allow fast and nonvolatile operation. However, building large memristive systems is still challenging since large analog circuits have to be designed and integrated. In this paper, we propose a novel solution - the implementation of digital standard cells by the means of RRAM devices. While this methodology is universal, with applications ranging from few-device-circuits to large macroblocks, we demonstrate it for a 2T2R-cell. The benefits of using RRAM devices are demonstrated by implementing a NAND standard cell merely consuming the area of two transistors. This cell is about 25 \% smaller than the equivalent CMOS NAND in the same technology. We use these cells to implement a half adder, beating the area of the equivalent CMOS implementation using more sophisticates gates by 15 \%. Lastly, we fully integrate this novel standard cell into a digital standard cell library and perform a synthesis and layout of a RISC-V CPU core.}, language = {en} } @misc{VishwakarmaFritscherHagelaueretal., author = {Vishwakarma, Abhinav and Fritscher, Markus and Hagelauer, Amelie and Reichenbach, Marc}, title = {An RRAM-based building block for reprogrammable non-uniform sampling ADCs}, series = {Information Technology : it}, volume = {65}, journal = {Information Technology : it}, number = {1-2}, issn = {2196-7032}, doi = {10.1515/itit-2023-0021}, pages = {39 -- 51}, language = {en} } @misc{SpetzlerFritscherParketal., author = {Spetzler, Benjamin and Fritscher, Markus and Park, Seongae and Kim, Nayoun and Wenger, Christian and Ziegler, Martin}, title = {AI-driven model for optimized pulse programming of memristive devices}, series = {APL Machine Learning}, volume = {3}, journal = {APL Machine Learning}, number = {2}, publisher = {AIP Publishing}, issn = {2770-9019}, doi = {10.1063/5.0251113}, pages = {1 -- 7}, abstract = {Next-generation artificial intelligence (AI) hardware based on memristive devices offers a promising approach to reducing the increasingly large energy consumption of AI applications. However, programming memristive AI hardware to achieve a desired synaptic weight configuration remains challenging because it requires accurate and energy-efficient algorithms for selecting the optimal weight-update pulses. Here, we present a computationally efficient AI model for predicting the weight update of memristive devices and guiding device programming. The synaptic weight-update behavior of bilayer HfO2/TiO2 memristive devices is characterized over a range of pulse parameters to provide experimental data for the AI model. Three different artificial neural network (ANN) configurations are trained and evaluated regarding the amount of training data required for accurate predictions and the computational costs. Finally, we apply the model to an antipulse weight-update process to demonstrate its performance. The results show that accurate and computationally inexpensive predictions are possible with comparatively few datasets and small ANNs. The normalized weight-update processes are predicted with accuracies comparable with larger model architectures but require only 896 floating point operations and 8.33 nJ per inference. This makes the model a promising candidate for integration into AI-driven device controllers as a precise and energy-efficient solution for memristive device programming.}, language = {en} } @misc{FritscherUhlmannOstrovskyyetal., author = {Fritscher, Markus and Uhlmann, Max and Ostrovskyy, Philip and Reiser, Daniel and Chen, Junchao and Wen, Jianan and Schulze, Carsten and Kahmen, Gerhard and Fey, Dietmar and Reichenbach, Marc and Krstic, Milos and Wenger, Christian}, title = {RISC-V CPU design using RRAM-CMOS standard cells}, series = {IEEE transactions on very large scale integration (VLSI) systems}, journal = {IEEE transactions on very large scale integration (VLSI) systems}, editor = {Wenger, Christian}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {1063-8210}, doi = {10.1109/TVLSI.2025.3554476}, pages = {1 -- 9}, abstract = {The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely, creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks, we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors, this enables us to construct a nand standard cell, which merely consumes the area of two transistors. This leads to a 25\% area reduction compared to an equivalent CMOS nand gate. We illustrate achievable area savings with a half-adder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7\% smaller area than the equivalent design using standard CMOS gates.}, language = {en} }