@misc{FritscherUhlmannOstrovskyyetal., author = {Fritscher, Markus and Uhlmann, Max and Ostrovskyy, Philip and Reiser, Daniel and Chen, Junchao and Wen, Jianan and Schulze, Carsten and Kahmen, Gerhard and Fey, Dietmar and Reichenbach, Marc and Krstic, Milos and Wenger, Christian}, title = {RISC-V CPU design using RRAM-CMOS standard cells}, series = {IEEE transactions on very large scale integration (VLSI) systems}, journal = {IEEE transactions on very large scale integration (VLSI) systems}, editor = {Wenger, Christian}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {1063-8210}, doi = {10.1109/TVLSI.2025.3554476}, pages = {1 -- 9}, abstract = {The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely, creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks, we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors, this enables us to construct a nand standard cell, which merely consumes the area of two transistors. This leads to a 25\% area reduction compared to an equivalent CMOS nand gate. We illustrate achievable area savings with a half-adder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7\% smaller area than the equivalent design using standard CMOS gates.}, language = {en} } @misc{AftowiczFritscherLehnigeretal., author = {Aftowicz, Marcin and Fritscher, Markus and Lehniger, Kai and Wenger, Christian and Langend{\"o}rfer, Peter and Brzozowski, Marcin}, title = {Hardware-friendly Nystr{\"o}m approximation for water treatment anomaly detection}, series = {IECON 2024 - 50th Annual Conference of the IEEE Industrial Electronics Society : proceedings}, journal = {IECON 2024 - 50th Annual Conference of the IEEE Industrial Electronics Society : proceedings}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {Piscataway, NJ}, isbn = {978-1-6654-6454-3}, doi = {10.1109/IECON55916.2024.10905880}, pages = {1 -- 7}, abstract = {This paper presents an approach to accelerate One-Class Support Vector Machines (SVM) using a hardware-friendly kernel that doesn't rely on multiplication operations, thus adaptable to hardware platforms. Leveraging Nystr{\"o}m approximation, we implemented a pipeline and compared its performance against a software implementation using libsvm. Furthermore, we evaluated the efficiency of our approach by deploying it on an FPGA. Our experiments, conducted on the SWaT dataset, demonstrate a 50x speedup using the FPGA implementation, achieving a classification time of 21 microseconds per instance. Importantly, we find no degradation in performance, as measured by the f-score of the attack class in the test set. This study explores the potential of hardware acceleration in optimizing anomaly detection systems for real-time applications.}, language = {en} }