@misc{CapelliniKozłowskiYamamotoetal., author = {Capellini, Giovanni and Kozłowski, Grzegorz and Yamamoto, Yuji and Lisker, Marco and Tillack, Bernd and Ghrib, A. and Kersauson, M. de and El Kurdi, M. and Boucaud, P. and Schroeder, Thomas}, title = {Tensile strained Ge layers obtained via Si-CMOS compatible approach}, series = {Journal of Applied Physics}, volume = {113}, journal = {Journal of Applied Physics}, number = {1}, pages = {013513-1 -- 013513-6}, language = {en} } @misc{LukosiusLippertDabrowskietal., author = {Lukosius, Mindaugas and Lippert, Gunther and Dabrowski, Jarek Marek and Kitzmann, Julia and Lisker, Marco and Kulse, Philipp and Kr{\"u}ger, Andreas and Fursenko, Oksana and Costina, Ioan and Trusch, Andreas and Yamamoto, Yuji and Wolff, Andre and Mai, Andreas and Schr{\"o}der, Thomas}, title = {Graphene Synthesis and Processing on Ge Substrates}, series = {ECS transactions}, volume = {75}, journal = {ECS transactions}, number = {8}, issn = {1938-6737}, doi = {10.1149/07508.0533ecst}, pages = {533 -- 540}, language = {en} } @misc{LukosiusDabrowskiLiskeretal., author = {Lukosius, Mindaugas and Dabrowski, Jarek Marek and Lisker, Marco and Kitzmann, Julia and Schulze, Sebastian and Lippert, Gunther and Fursenko, Oksana and Yamamoto, Yuji and Schubert, Markus Andreas and Krause, Hans-Michael and Wolff, Andre and Mai, A. and Schr{\"o}der, Thomas and Lupina, Grzegorz}, title = {Metal-free, CVD Graphene synthesis on 200 mm Ge / Si(001) substrates}, series = {ACS Applied Materials and Interfaces}, volume = {8}, journal = {ACS Applied Materials and Interfaces}, number = {49}, issn = {1944-8244}, doi = {10.1021/acsami.6b11397}, pages = {33786 -- 33793}, language = {en} } @misc{MahadevaiahPerezLiskeretal., author = {Mahadevaiah, Mamathamba Kalishettyhalli and P{\´e}rez, Eduardo and Lisker, Marco and Schubert, Markus Andreas and Perez-Bosch Quesada, Emilio and Wenger, Christian and Mai, Andreas}, title = {Modulating the Filamentary-Based Resistive Switching Properties of HfO2 Memristive Devices by Adding Al2O3 Layers}, series = {Electronics : open access journal}, volume = {11}, journal = {Electronics : open access journal}, number = {10}, issn = {2079-9292}, doi = {10.3390/electronics11101540}, pages = {14}, abstract = {The resistive switching properties of HfO2 based 1T-1R memristive devices are electrically modified by adding ultra-thin layers of Al2O3 into the memristive device. Three different types of memristive stacks are fabricated in the 130 nm CMOS technology of IHP. The switching properties of the memristive devices are discussed with respect to forming voltages, low resistance state and high resistance state characteristics and their variabilities. The experimental I-V characteristics of set and reset operations are evaluated by using the quantum point contact model. The properties of the conduction filament in the on and off states of the memristive devices are discussed with respect to the model parameters obtained from the QPC fit.}, language = {en} } @misc{LukosiusLukoseLiskeretal., author = {Lukosius, Mindaugas and Lukose, Rasuolė and Lisker, Marco and Luongo, G. and Elviretti, M. and Mai, Andreas and Wenger, Christian}, title = {Graphene Research in 200 mm CMOS Pilot Line}, series = {45th Jubilee International Convention on Information, Communication and Electronic Technology (MIPRO), 2022}, journal = {45th Jubilee International Convention on Information, Communication and Electronic Technology (MIPRO), 2022}, isbn = {978-953-233-103-5}, issn = {2623-8764}, doi = {10.23919/MIPRO55190.2022.9803362}, pages = {113 -- 117}, abstract = {Due to the unique electronic structures, graphene and other 2D Materials are considered as materials which can enable and extend the functionalities and performance in a large variety of applications, among them in microelectronics. At this point, the investigation and preparation of graphene devices in conditions resembling as close as possible the Si technology environment is of highest importance.Towards these goals, this paper focuses on the full spectra of graphene research aspects in 200mm pilot line. We investigated different process module developments such as CMOS compatible growth of high quality graphene on germanium and its growth mechanisms, transfer related challenges on target substrates, patterning, passivation and various concepts of contacting of graphene on a full 200 mm wafers. Finally, we fabricated proof-of-concept test structures e.g. TLM, Hall bars and capacitor structures to prove the feasibility of graphene processing in the pilot line of IHP.}, language = {en} } @misc{DoraiSwamyReddyPerezBaronietal., author = {Dorai Swamy Reddy, Keerthi and P{\´e}rez, Eduardo and Baroni, Andrea and Mahadevaiah, Mamathamba Kalishettyhalli and Marschmeyer, Steffen and Fraschke, Mirko and Lisker, Marco and Wenger, Christian and Mai, Andreas}, title = {Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance}, series = {The European Physical Journal B}, volume = {97}, journal = {The European Physical Journal B}, publisher = {Springer Science and Business Media LLC}, issn = {1434-6028}, doi = {10.1140/epjb/s10051-024-00821-1}, pages = {9}, abstract = {Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal-insulator-metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2 dielectric thickness from 8 nm to 5 nm. Additionally, 5\% Al-doped 4 nm HfO2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology.}, language = {en} } @misc{CapistaLukoseMajnoonetal., author = {Capista, Daniele and Lukose, Rasuole and Majnoon, Farnaz and Lisker, Marco and Wenger, Christian and Lukosius, Mindaugas}, title = {Optimization of the metal deposition process for the accurate estimation of Low Metal-Graphene Contact-Resistance}, series = {47th MIPRO ICT and Electronics Convention (MIPRO), 20-24 May 2024, Opatija, Croatia}, journal = {47th MIPRO ICT and Electronics Convention (MIPRO), 20-24 May 2024, Opatija, Croatia}, isbn = {979-8-3503-8250-1}, issn = {2623-8764}, doi = {10.1109/MIPRO60963.2024.10569895}, pages = {5}, language = {en} } @misc{LukosiusLukoseDubeyetal., author = {Lukosius, Mindaugas and Lukose, Rasuolė and Dubey, P. K. and Raju, A. I. and Capista, Daniele and Lisker, Marco and Mai, A. and Wenger, Christian}, title = {Graphene for photonic applications}, series = {2024 47th MIPRO ICT and Electronics Convention (MIPRO)}, journal = {2024 47th MIPRO ICT and Electronics Convention (MIPRO)}, publisher = {IEEE}, isbn = {979-8-3503-8250-1}, issn = {2623-8764}, doi = {10.1109/MIPRO60963.2024.10569652}, pages = {1614 -- 1618}, abstract = {Integrating graphene into Silicon Complementary Metal-Oxide-Semiconductor (CMOS) technology for photonic applications holds immense promise, but it encounters challenges in establishing large-scale graphene processes. These challenges encompass growth through techniques like Chemical Vapor Deposition (CVD), transfer, encapsulation, and contact formation within a routine 200mm wafer pilot line typically utilized for integrated circuit fabrication. This study is dedicated to exploring various facets of graphene research within a 200 mm pilot line, with a focus on overcoming challenges through the fabrication of proof-of-concept photonic graphene-based devices. The synthesis of graphene targeted epi-Ge(100)/Si(100) substrates, grown within the IHP pilot line, showcasing the potential for high-quality graphene deposition across 200mm wafers. Alternatively, employing different orientations such as (110) has been explored to enhance graphene mobility, achieving a remarkable mobility of 2300 cm 2 /Vs at present. The study systematically investigates graphene quality, thickness, and homogeneity utilizing techniques such as Raman spectroscopy, Atomic Force Microscopy (AFM), and Scanning Electron Microscopy (SEM). Additionally, simulations and fabrication of the graphene ring modulators have been conducted at both the component and device levels, incorporating realistic graphene properties. These results indicate a modulation depth of 1.6 dB/μm and a 3dB bandwidth of 7 GHz, showcasing the potential of graphene-based photonic devices for high-speed communication applications.}, language = {en} } @misc{TetznerSeifertSkibitzkietal., author = {Tetzner, Henriette and Seifert, W. and Skibitzki, Oliver and Yamamoto, Yuji and Lisker, Marco and Mirza, M. M. and Fischer, Inga Anita and Paul, Douglas J. and De Seta, Monica and Capellini, Giovanni}, title = {Unintentional p-type conductivity in intrinsic Ge-rich SiGe/Ge heterostructures grown on Si(001)}, series = {Applied Physics Letter}, volume = {122}, journal = {Applied Physics Letter}, number = {24}, issn = {1077-3118}, doi = {10.1063/5.0152962}, language = {en} } @misc{CapistaLukoseMajnoonetal., author = {Capista, Daniele and Lukose, Rasuole and Majnoon, Farnaz and Lisker, Marco and Wenger, Christian and Lukosius, Mindaugas}, title = {Study on the metal -graphene contact resistance achieved with one -dimensional contact architecture}, series = {IEEE Nanotechnology Materials and Devices Conference (NMDC 2023), Paestum, Italy, 22-25 October 2023}, journal = {IEEE Nanotechnology Materials and Devices Conference (NMDC 2023), Paestum, Italy, 22-25 October 2023}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-3546-0}, doi = {10.1109/NMDC57951.2023.10343775}, pages = {118 -- 119}, abstract = {Graphene has always been considered as one of the materials with the greatest potential for the realization of improved microelectronic and photonic devices. But to actually reach its full potential in Si CMOS technology, graphene -based devices need to overcome different challenges. They do not only need to have better performances than standard devices, but they also need to be compatible with the production of standard Si based devices. To address the first challenge the main route requires the optimization of the contact resistance, that highly reduces the devices performance, while the second challenges requires the integration of graphene inside the standard production lines used for microelectronic. In this work we used an 8" wafer pilot -line to realize our devices and we studied the behavior of the contact resistance between metal and graphene obtained by one -dimensional contact architecture between the two materials. The contact resistance has been measured by means of Transmission Line Method (TLM) with several contact patterning.}, language = {en} }