@misc{LehnigerLangendoerfer, author = {Lehniger, Kai and Langend{\"o}rfer, Peter}, title = {Investigating compact shadow stacks for the Xtensa LX architecture}, series = {2025 14th Mediterranean Conference on Embedded Computing (MECO)}, journal = {2025 14th Mediterranean Conference on Embedded Computing (MECO)}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {979-8-3315-1341-2}, doi = {10.1109/MECO66322.2025.11049161}, pages = {1 -- 6}, abstract = {This paper presents a compact shadow stack implementation for the Xtensa LX architecture, implemented for an ESP32 microcontroller. The implementation is done by changing the register window exception handlers in the FreeRTOS operating system. In a second implementation the shadow stack was extended to all register values, not just return addresses. This not only increases security but also performance, reducing the overhead from 17.220\% to 13.529\%, in the worst-case-scenario. The paper also suggests future improvements that could decrease the overhead even further.}, language = {en} } @misc{LehnigerLangendorfer, author = {Lehniger, Kai and Langendorfer, Peter}, title = {Elevating parallel shadow stack concepts for architectures with register windows}, series = {IEEE transactions on dependable and secure computing}, journal = {IEEE transactions on dependable and secure computing}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {Piscataway, NJ}, issn = {1545-5971}, doi = {10.1109/TDSC.2025.3604556}, pages = {1 -- 18}, abstract = {Register windows are a processor feature that was originally developed to reduce the frequency for register spilling. This paper investigates how this mechanism can be used to implement a parallel shadow stack to protect return addresses from being corrupted. Furthermore, multiple improvements based on properties directly following the usage of register windows are proposed. Different configurations of parallel shadow stacks are evaluated based on prototype implementations on an ESP32 microcontroller and tested with different benchmarks. Performance overheads below 0.01\% for CoreMark, below 3\% for the worst case in MbedsTLS, and a worst case scenario of 22.153\% for a recursive function show that our concepts are able to be efficiently developed even for embedded devices like the ESP32.}, language = {en} }