@misc{PidvalnyiKostenkoSudakovetal., author = {Pidvalnyi, Illia and Kostenko, Anna and Sudakov, Oleksandr and Isaev, Dmytro and Maximyuk, Oleksandr and Krishtal, Oleg and Iegorova, Olena and Kabin, Ievgen and Dyka, Zoya and Ortmann, Steffen and Langend{\"o}rfer, Peter}, title = {Classification of epileptic seizures by simple machine learning techniques : application to animals' electroencephalography signals}, series = {IEEE access}, volume = {13}, journal = {IEEE access}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {Piscataway, NJ}, issn = {2169-3536}, doi = {10.1109/ACCESS.2025.3527866}, pages = {8951 -- 8962}, abstract = {Detection and prediction of the onset of seizures are among the most challenging problems in epilepsy diagnostics and treatment. Small electronic devices capable of doing that will improve the quality of life for epilepsy patients while also open new opportunities for pharmacological intervention. This paper presents a novel approach using machine learning techniques to detect seizures onset using intracranial electroencephalography (EEG) signals. The proposed approach was tested on intracranial EEG data recorded in rats with pilocarpine model of temporal lobe epilepsy. A principal component analysis was applied for feature selection before using a support vector machine for the detection of seizures. Hjorth's parameters and Daubechies discrete wavelet transform coefficients were found to be the most informative features of EEG data. We found that the support vector machine approach had a classification sensitivity of 90\% and a specificity of 74\% for detecting ictal episodes. Changing the epoch parameter from one to twenty-one seconds results in changing the redistribution of principal components' values to 10\% but does not affect the classification result. Support vector machines are accessible and convenient methods for classification that have achieved promising classification quality, and are rather lightweight compared to other machine learning methods. So we suggest their future use in mobile devices for early epileptic seizure and preictal episode detection.}, language = {en} } @misc{AftowiczFritscherLehnigeretal., author = {Aftowicz, Marcin and Fritscher, Markus and Lehniger, Kai and Wenger, Christian and Langend{\"o}rfer, Peter and Brzozowski, Marcin}, title = {Hardware-friendly Nystr{\"o}m approximation for water treatment anomaly detection}, series = {IECON 2024 - 50th Annual Conference of the IEEE Industrial Electronics Society : proceedings}, journal = {IECON 2024 - 50th Annual Conference of the IEEE Industrial Electronics Society : proceedings}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {Piscataway, NJ}, isbn = {978-1-6654-6454-3}, doi = {10.1109/IECON55916.2024.10905880}, pages = {1 -- 7}, abstract = {This paper presents an approach to accelerate One-Class Support Vector Machines (SVM) using a hardware-friendly kernel that doesn't rely on multiplication operations, thus adaptable to hardware platforms. Leveraging Nystr{\"o}m approximation, we implemented a pipeline and compared its performance against a software implementation using libsvm. Furthermore, we evaluated the efficiency of our approach by deploying it on an FPGA. Our experiments, conducted on the SWaT dataset, demonstrate a 50x speedup using the FPGA implementation, achieving a classification time of 21 microseconds per instance. Importantly, we find no degradation in performance, as measured by the f-score of the attack class in the test set. This study explores the potential of hardware acceleration in optimizing anomaly detection systems for real-time applications.}, language = {en} } @misc{LehnigerLangendorfer, author = {Lehniger, Kai and Langendorfer, Peter}, title = {Elevating parallel shadow stack concepts for architectures with register windows}, series = {IEEE transactions on dependable and secure computing}, journal = {IEEE transactions on dependable and secure computing}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {Piscataway, NJ}, issn = {1545-5971}, doi = {10.1109/TDSC.2025.3604556}, pages = {1 -- 18}, abstract = {Register windows are a processor feature that was originally developed to reduce the frequency for register spilling. This paper investigates how this mechanism can be used to implement a parallel shadow stack to protect return addresses from being corrupted. Furthermore, multiple improvements based on properties directly following the usage of register windows are proposed. Different configurations of parallel shadow stacks are evaluated based on prototype implementations on an ESP32 microcontroller and tested with different benchmarks. Performance overheads below 0.01\% for CoreMark, below 3\% for the worst case in MbedsTLS, and a worst case scenario of 22.153\% for a recursive function show that our concepts are able to be efficiently developed even for embedded devices like the ESP32.}, language = {en} }