@misc{FritscherKnoedtelMallahetal., author = {Fritscher, Markus and Kn{\"o}dtel, Johannes and Mallah, Maen and Pechmann, Stefan and Perez-Bosch Quesada, Emilio and Rizzi, Tommaso and Wenger, Christian and Reichenbach, Marc}, title = {Mitigating the Effects of RRAM Process Variation on the Accuracy of Artifical Neural Networks}, series = {Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2021. Lecture Notes in Computer Science}, journal = {Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2021. Lecture Notes in Computer Science}, publisher = {Springer}, isbn = {978-3-031-04579-0}, issn = {0302-9743}, doi = {10.1007/978-3-031-04580-6_27}, pages = {401 -- 417}, abstract = {Weight storage is a key challenge in the efficient implementation of artificial neural networks. Novel memory technologies such as RRAM are able to greatly improve density and introduce non-volatility and multibit capabilities to this component of ANN accelerators. The usage of RRAM in this domain comes with downsides, mainly caused by cycle-to-cycle and device-to-device variability leading to erroneous readouts, greatly affecting digital systems. ANNs have the ability to compensate for this by their inherent redundancy and usually exhibit a gradual deterioration in the accuracy of the task at hand. This means, that slight error rates can be acceptable for weight storage in an ANN accelerator. In this work we link device-to-device variability to the accuracy of an ANN for such an accelerator. From this study, we can estimate how strongly a certain net is affected by a certain device parameter variability. This methodology is then used to present three mitigation strategies and to evaluate how they affect the reaction of the network to variability: a) Dropout Layers b) Fault-Aware Training c) Redundancy. These mitigations are then evaluated by their ability to improve accuracy and to lower hardware overhead by providing data for a real-word example. We improved this network's resilience in such a way that it could tolerate double the variation in one of the device parameters (standard deviation of the oxide thickness can be 0.4 nm instead of 0.2 nm while maintaining sufficient accuracy.)}, language = {en} } @misc{KnoedtelMunozHernandezLehnertetal., author = {Kn{\"o}dtel, Johannes and Munoz Hernandez, Hector Gerardo and Lehnert, Alexander and Thieu, Gia Bao and Gesper, Sven and Pay{\´a}-Vay{\´a}, Guillermo and Reichenbach, Marc}, title = {TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs}, series = {Applied Reconfigurable Computing. Architectures, Tools, and Applications, 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023, Proceedings}, journal = {Applied Reconfigurable Computing. Architectures, Tools, and Applications, 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023, Proceedings}, editor = {Palumbo, Francesca and Keramidas, Georgios and Voros, Nikolaos and Diniz, Pedro C.}, publisher = {Springer}, address = {Cham}, isbn = {978-3-031-42920-0}, doi = {10.1007/978-3-031-42921-7_21}, pages = {307 -- 321}, language = {en} } @misc{KnoedtelRachujReichenbach, author = {Kn{\"o}dtel, Johannes and Rachuj, Sebastian and Reichenbach, Marc}, title = {Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the best?}, series = {25th Euromicro Conference on Digital System Design (DSD), 31 August 2022 - 02 September 2022, Maspalomas, Spain}, journal = {25th Euromicro Conference on Digital System Design (DSD), 31 August 2022 - 02 September 2022, Maspalomas, Spain}, publisher = {IEEE}, doi = {10.1109/DSD57027.2022.00041}, pages = {247 -- 253}, language = {en} }