@inproceedings{FrickeWernerShahinetal., author = {Fricke, Florian and Werner, Andr{\´e} and Shahin, Keyvan and H{\"u}bner, Michael}, title = {CGRA Tool Flow for Fast Run-Time Reconfiguration}, series = {Proceedings, 14th International Symposium on Applied Reconfigurable Computing, Santorini, Greece, May 2-4, 2018}, booktitle = {Proceedings, 14th International Symposium on Applied Reconfigurable Computing, Santorini, Greece, May 2-4, 2018}, editor = {Voros, Nikolaos and H{\"u}bner, Michael and Keramidas, Georgios and G{\"o}hringer, Diana and Antonopoulos, Christos and Diniz, Pedro C.}, publisher = {Springer}, address = {Cham}, isbn = {978-3-319-78889-0}, doi = {10.1007/978-3-319-78890-6_53}, pages = {661 -- 672}, language = {en} } @misc{WernerFrickeShahinetal., author = {Werner, Andr{\´e} and Fricke, Florian and Shahin, Keyvan and Werner, Florian and H{\"u}bner, Michael}, title = {Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms}, series = {Applied Reconfigurable Computing, 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9-11, 2019, Proceedings}, journal = {Applied Reconfigurable Computing, 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9-11, 2019, Proceedings}, editor = {Hochberger, Christian and Nelson, Brent and Koch, Andreas and Woods, Roger and Diniz, Pedro C.}, publisher = {Springer}, address = {Cham}, isbn = {978-3-030-17226-8}, issn = {0302-9743}, doi = {0.1007/978-3-030-17227-5_20}, pages = {277 -- 291}, language = {en} } @misc{FrickeMahmoodHoffmannetal., author = {Fricke, Florian and Mahmood, Safdar and Hoffmann, Javier Eduardo and Ali, Muhammad and Shahin, Keyvan and H{\"u}bner, Michael and G{\"o}hringer, Diana}, title = {Domain Adaptive Processor Architectures}, series = {Kommunikation und Bildverarbeitung in der Automation}, journal = {Kommunikation und Bildverarbeitung in der Automation}, isbn = {978-3-662-59895-5}, issn = {2522-8579}, doi = {10.1007/978-3-662-59895-5_23}, pages = {315 -- 330}, language = {en} } @misc{FrickeWernerShahinetal., author = {Fricke, Florian and Werner, Andr{\´e} and Shahin, Keyvan and Werner, Florian and H{\"u}bner, Michael}, title = {Automatic Tool-Flow for Mapping Applications to an Application-Specific CGRA Architecture}, series = {IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum (IPDPSW)}, journal = {IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum (IPDPSW)}, isbn = {978-1-7281-3510-6}, doi = {10.1109/IPDPSW.2019.00033}, pages = {147 -- 154}, language = {en} } @misc{ShahinRottaArchilaetal., author = {Shahin, Keyvan and Rotta, Randolf and Archila, Oscar and Mykytyn, Pavlo and Nattke, Matthias and Reichenbach, Marc and Nolte, J{\"o}rg and Natarov, Roman}, title = {A Modular Communication Architecture for Adaptive UAV Swarms}, series = {2023 IEEE International Conference on Omni-layer Intelligent Systems (COINS)}, journal = {2023 IEEE International Conference on Omni-layer Intelligent Systems (COINS)}, publisher = {IEEE}, address = {Berlin}, isbn = {979-8-3503-4647-3}, doi = {10.1109/COINS57856.2023.10189245}, pages = {6}, abstract = {Small Unmanned Aerial Vehicles (UAVs) have vast application potential from industrial logistics and disaster monitoring to smart farming, for example, to create maps with Normalized Difference Vegetation Index (NDVI) cameras and AI-based image classification or the precision spot application of fertilizers. Operating multiple UAVs in parallel, including those with different specializations, enables efficient coverage of large areas. While existing research focused mainly on predefined flight formations for swarms or autonomous missions for single UAVs, the focus of this work is on multiple UAVs with individually adaptable missions. We derive communication system requirements from swarm coordination algorithms and present a respective design. The resulting modular architecture enables future research on autonomous adaptive UAV swarms and their use as flying sensor platforms.}, language = {en} } @misc{SridharShahinBreussetal., author = {Sridhar, Vivek and Shahin, Keyvan and Breuß, Michael and Reichenbach, Marc}, title = {The Polynomial Connection between Morphological Dilation and Discrete Convolution}, series = {arXiv}, journal = {arXiv}, doi = {10.48550/arXiv.2305.03018}, pages = {1 -- 11}, language = {en} } @misc{ShahinHuebnerHerglotz, author = {Shahin, Keyvan and H{\"u}bner, Michael and Herglotz, Christian}, title = {A width-configurable hardware approach for accelerating fixed-point simulation}, series = {IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, journal = {IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {979-8-3315-3477-6}, issn = {2159-3477}, doi = {10.1109/ISVLSI65124.2025.11130205}, pages = {6}, abstract = {Fixed-point simulation is a critical step in the design flow of Digital Signal Processing (DSP) systems and consumes a significant portion of the overall development time. This work proposes a novel hardware-based approach to improve the performance of fixed-point simulation through a widthconfigurable architecture implemented on Field-Programmable Gate Arrays (FPGAs). To our knowledge, this is the first reported hardware-based solution for fixed-point simulation reported in the literature, which provides substantial speedup compared to traditional software-based approaches. The presented approach utilizes High-Level Synthesis (HLS) tools to create modular, reusable components that enhance the design reusability. This approach accelerates fixed-point simulation for various applications, requiring only minor modifications to the application code to utilize it. By incorporating simulation capabilities within reusable functions, this work improves the efficiency and adaptability of the fixed-point simulation process. Implementation results for two FIR filter applications show that the proposed methodology is superior to traditional software-based approaches in reducing simulation time by two orders of magnitude and thus has the potential to improve the productivity of the DSP system design flow.}, language = {en} } @misc{ShahinHuebner, author = {Shahin, Keyvan and H{\"u}bner, Michael}, title = {Accelerating fixed-point simulations using width reconfigurable hardware architectures}, series = {31st International Conference on Field-Programmable Logic and Applications (FPL), Dresden, Germany, 30 August-3 September 2021}, journal = {31st International Conference on Field-Programmable Logic and Applications (FPL), Dresden, Germany, 30 August-3 September 2021}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-6654-3759-2}, issn = {1946-1488}, doi = {10.1109/FPL53798.2021.00055}, pages = {275 -- 276}, abstract = {Digital Signal Processing (DSP) systems can be described using either fixed-point or floating-point for their numeric representations. As the general computers use floating-point representation, software-based simulation tools used for modeling and simulation of the arithmetic operations in DSP systems, use floating-point representation as well. However, synthesizing customized hardware for fixed-point arithmetic operations for FPGAs or ASICs is more efficient compared to their floating-point counterparts. Thus it is necessary to convert the representation of a floating-point simulated algorithm on MATLAB for example, to a fixed-point representation which is more suitable for hardware implementation. While former approaches for this conversion step have always been software-based, like on MATLAB itself, this paper presents a new approach to show the possibility of accelerating it by using hardware width reconfigurable designs.}, language = {en} } @misc{MunozHernandezAliShahinetal., author = {Mu{\~n}oz-Hernandez, Hector Gerardo and Ali, Muhammad and Shahin, Keyvan and Siyavashi, Alireza and G{\"o}hringer, Diana and Reichenbach, Marc and Herglotz, Christian and H{\"u}bner, Michael}, title = {Towards complete open-source environments : FPGA-based GPU overlay controlled by RISC-V}, series = {Architecture of computing systems : 38th International Conference, ARCS 2025 Kiel, Germany, April 22-24, 2025, proceedings}, journal = {Architecture of computing systems : 38th International Conference, ARCS 2025 Kiel, Germany, April 22-24, 2025, proceedings}, publisher = {Springer}, address = {Berlin}, isbn = {978-3-032-03280-5}, issn = {0302-9743}, doi = {https://doi.org/10.1007/978-3-032-03281-2_7}, pages = {94 -- 108}, abstract = {Image and signal processing applications have been widely implemented in Field Programmable Gate Arrays (FPGAs) and Graphical Processing Units (GPUs) due to their energy efficiency and performance, respectively. GPUs provide high data processing parallelism and are usually chosen to accelerate applications where low energy consumption is not a high priority. On the other hand, FPGAs are more tailored to hardware solutions due to their reconfigurability, but they struggle to outperform GPUs in data throughput. Soft IP cores implemented on reconfigurable hardware, are an alternative offering advantages from both worlds. Some of these soft-core solutions offer an entire environment that includes scripts to automate their implementation, custom compilers, and other diverse tools. Unfortunately, some of these soft-cores are dependent on proprietary Intellectual Property (IP) or require hardware expertise to use properly. In this work, we propose an extended version of a popular open-source soft GPU, which can now run alongside a soft RISC-V core, and with High-Bandwidth memory (HBM2) compatibility. Previously, this soft GPU was only ready to be deployed in boards with a hard ARM core, but now it can be easily used in FPGAs without this requirement. We also provide an evaluation of how the soft GPU performs with respect to the pure RISC-V core, and a hard ARM core achieving geometric mean speed-ups of 114.60x and 19.72x respectively when performing some image and signal processing applications. Finally, we demonstrate how our soft GPU benefits from the HBM integration.}, language = {en} } @misc{HerglotzJabłońskiKarnapkeetal., author = {Herglotz, Christian and Jabłoński, Ireneusz and Karnapke, Reinhardt and Shahin, Keyvan and Reichenbach, Marc}, title = {Designing intelligent sensor networks : a comprehensive survey of sensing, edge AI, and 5G+/6G connectivity}, series = {IEEE access}, volume = {13}, journal = {IEEE access}, publisher = {IEEE}, address = {Piscataway, NJ}, issn = {2169-3536}, doi = {10.1109/ACCESS.2025.3615205}, pages = {172306 -- 172325}, abstract = {With the advent of advanced transmission technologies, powerful neural-network architectures, and the availability of cheap sensing solutions, new paradigms for monitoring, controlling, and optimizing any automated system are appearing. While traditionally, sensors simply provided visual or acoustic feedback to human operators of such systems, nowadays, autonomous systems more and more rely on the automatic sensing and processing of such data to react and adapt their control mechanisms. In such complex control systems, sensor networks play a vital role. In this paper, we assess the state of the art in the three main components used within sensor networks: smart sensing elements, transmission technologies, and processing technologies. Concerning the latter, more and more artificial intelligence-based methods are developed and applied turning smart sensor networks into intelligent or even cognitive sensor networks. For the development of such sensing systems, a high variety of performance metrics could be important to the designer. This paper discusses the vast design space for intelligent sensor networks and provides guidance and directions on how to construct future intelligent sensor networks efficiently.}, language = {en} }