@misc{WimmerKrishnegowdaMethfesseletal., author = {Wimmer, Lara and Krishnegowda, Karthik and Methfessel, Michael and Kraemer, Rolf}, title = {PSSS Radio Communication Technology for High Data Rates}, language = {en} } @misc{WimmerKrishnegowdaMethfesseletal., author = {Wimmer, Lara and Krishnegowda, Karthik and Methfessel, Michael and Kraemer, Rolf}, title = {Verfahren zur Synchronisation in einem PSSS Closed-Loop Funksystem}, language = {de} } @incollection{RehmanJavedScheyttBammidietal., author = {Rehman Javed, Abdul and Scheytt, J. Christoph and Bammidi, Eswara Rao and Kallfass, Ingmar and Krishnegowda, Karthik and Kraemer, Rolf}, title = {Real100G.COM}, series = {Wireless 100 Gbps and beyond : architectures, spproaches and findings of German Research Foundation (DFG) priority programme SPP 1655}, booktitle = {Wireless 100 Gbps and beyond : architectures, spproaches and findings of German Research Foundation (DFG) priority programme SPP 1655}, editor = {Kraemer, Rolf and Scholz, Stefan}, edition = {1. Auflage}, publisher = {IHP GmbH}, address = {Frankfurt (Oder)}, isbn = {978-3-96439-003-5}, pages = {231 -- 293}, language = {en} } @incollection{ScheyttRehmanJavedBhutanietal., author = {Scheytt, J. Christoph and Rehman Javed, Abdul and Bhutani, Akanksha and Zwick, Thomas and Kallfass, Ingmar and Bammidi, Eswara Rao and Krishnegowda, Karthik and Kraemer, Rolf}, title = {Real100G - Ultrabroadband Wireless Communication at High mm-Wave Frequencies}, series = {Wireless 100 Gbps and beyond : architectures, spproaches and findings of German Research Foundation (DFG) priority programme SPP 1655}, booktitle = {Wireless 100 Gbps and beyond : architectures, spproaches and findings of German Research Foundation (DFG) priority programme SPP 1655}, editor = {Kraemer, Rolf and Scholz, Stefan}, edition = {1. Auflage}, publisher = {IHP GmbH}, address = {Frankfurt (Oder)}, isbn = {978-3-96439-003-5}, pages = {213 -- 230}, language = {en} } @misc{WenBaroniPerezetal., author = {Wen, Jianan and Baroni, Andrea and Perez, Eduardo and Uhlmann, Max and Fritscher, Markus and KrishneGowda, Karthik and Ulbricht, Markus and Wenger, Christian and Krstic, Milos}, title = {Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator}, series = {2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}, journal = {2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}, publisher = {IEEE}, isbn = {978-3-9819263-8-5}, issn = {1558-1101}, doi = {10.23919/DATE58400.2024.10546709}, pages = {1 -- 6}, abstract = {The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 \% and 18 \%, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83\% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero.}, language = {en} }