@misc{DziallasFatemiKorndoerferetal., author = {Dziallas, Giannino and Fatemi, Adel and Kornd{\"o}rfer, Falk and Peczek, Anna and Kissinger, Dietmar and Zimmermann, Lars and Malignaggi, Andrea and Kahmen, Gerhard}, title = {A Monolithically Integrated Optical Bandpass Receiver in 0.25μm SiGe BiCMOS Technology for Microwave-Photonic Applications}, series = {2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), November 9-11, 2020 ONLINE}, journal = {2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), November 9-11, 2020 ONLINE}, isbn = {978-1-7281-8436-4}, doi = {10.1109/A-SSCC48613.2020.9336119}, pages = {4}, language = {en} } @misc{FritscherSinghRizzietal., author = {Fritscher, Markus and Singh, Simranjeet and Rizzi, Tommaso and Baroni, Andrea and Reiser, Daniel and Mallah, Maen and Hartmann, David and Bende, Ankit and Kempen, Tim and Uhlmann, Max and Kahmen, Gerhard and Fey, Dietmar and Rana, Vikas and Menzel, Stephan and Reichenbach, Marc and Krstic, Milos and Merchant, Farhad and Wenger, Christian}, title = {A flexible and fast digital twin for RRAM systems applied for training resilient neural networks}, series = {Scientific Reports}, volume = {14}, journal = {Scientific Reports}, number = {1}, publisher = {Springer Science and Business Media LLC}, issn = {2045-2322}, doi = {10.1038/s41598-024-73439-z}, pages = {13}, abstract = {Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the "ideal memristor" which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a "push button" modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).}, language = {en} } @misc{FritscherUhlmannOstrovskyyetal., author = {Fritscher, Markus and Uhlmann, Max and Ostrovskyy, Philip and Reiser, Daniel and Chen, Junchao and Schubert, Andreas and Schulze, Carsten and Kahmen, Gerhard and Fey, Dietmar and Reichenbach, Marc and Krstic, Milos and Wenger, Christian}, title = {Area-efficient digital design using RRAM-CMOS standard cells}, series = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, volume = {18}, journal = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, publisher = {IEEE}, isbn = {979-8-3503-5411-9}, issn = {2159-3477}, doi = {10.1109/ISVLSI61997.2024.00026}, pages = {81 -- 87}, abstract = {Extending the scalability of digital integrated circuits through novel device concepts is an attractive option. Among these concepts, resistive random access memory (RRAM) devices allow fast and nonvolatile operation. However, building large memristive systems is still challenging since large analog circuits have to be designed and integrated. In this paper, we propose a novel solution - the implementation of digital standard cells by the means of RRAM devices. While this methodology is universal, with applications ranging from few-device-circuits to large macroblocks, we demonstrate it for a 2T2R-cell. The benefits of using RRAM devices are demonstrated by implementing a NAND standard cell merely consuming the area of two transistors. This cell is about 25 \% smaller than the equivalent CMOS NAND in the same technology. We use these cells to implement a half adder, beating the area of the equivalent CMOS implementation using more sophisticates gates by 15 \%. Lastly, we fully integrate this novel standard cell into a digital standard cell library and perform a synthesis and layout of a RISC-V CPU core.}, language = {en} } @misc{UhlmannRizziWenetal., author = {Uhlmann, Max and Rizzi, Tommaso and Wen, Jianan and P{\´e}rez-Bosch Quesada, Emilio and Al Beattie, Bakr and Ochs, Karlheinz and P{\´e}rez, Eduardo and Ostrovskyy, Philip and Carta, Corrado and Wenger, Christian and Kahmen, Gerhard}, title = {LUT-based RRAM model for neural accelerator circuit simulation}, series = {Proceedings of the 18th ACM International Symposium on Nanoscale Architectures}, journal = {Proceedings of the 18th ACM International Symposium on Nanoscale Architectures}, publisher = {ACM}, address = {New York, NY, USA}, doi = {10.1145/3611315.3633273}, pages = {1 -- 6}, abstract = {Neural hardware accelerators have been proven to be energy-efficient when used to solve tasks which can be mapped into an artificial neural network (ANN) structure. Resistive random-access memories (RRAMs) are currently under investigation together with several different memristive devices as promising technologies to build such accelerators combined together with complementary metal-oxide semiconductor (CMOS)-technologies in integrated circuits (ICs). While many research groups are actively developing sophisticated physical-based representations to better understand the underlying phenomena characterizing these devices, not much work has been dedicated to exploit the trade-off between simulation time and accuracy in the definition of low computational demanding models suitable to be used at many abstraction layers. Indeed, the design of complex mixed-signal systems as a neural hardware accelerators requires frequent interaction between the application- and the circuit-level that can be enabled only with the support of accurate and fast-simulating devices' models. In this work, we propose a solution to fill the aforementioned gap with a lookup table (LUT)-based Verilog-A model of IHP's 1-transistor-1-RRAM (1T1R) cell. In addition, the implementation challenges of conveying the communication between the abstract ANN simulation and the circuital analysis are tackled with a design flow for resistive neural hardware accelerators that features a custom Python wrapper. As a demonstration of the proposed design flow and 1T1R model, an ANN for the MNIST handwritten digit recognition task is assessed with the last layer verified in circuit simulation. The obtained recognition confidence intervals show a considerable discrepancy between the purely application-level PyTorch simulation and the proposed design flow which spans across the abstraction layers down to the circuital analysis.}, language = {en} } @misc{Kahmen, author = {Kahmen, Gerhard}, title = {SiGe BiCMOS as Enabling Technology for Next Generation RF \& THz Systems}, series = {EuMIC 2021 Abstract Cards, 16th European Microwave Integrated Circuits Conference (EuMIC), London, United Kingdom, 2022}, journal = {EuMIC 2021 Abstract Cards, 16th European Microwave Integrated Circuits Conference (EuMIC), London, United Kingdom, 2022}, publisher = {IEEE}, address = {Piscataway, NJ}, doi = {10.23919/EuMIC50153.2022.9783893}, pages = {S. 21}, language = {en} } @misc{SuetbasNgWesseletal., author = {S{\"u}tbas, Batuhan and Ng, Herman Jalli and Wessel, Jan and K{\"o}lpin, Alexander and Kahmen, Gerhard}, title = {A V-band Low-Power and Compact Down-Conversion Mixer with Low LO Power in 130-nm SiGe BiCMOS Technology}, series = {16th European Microwave Integrated Circuits Conference (EuMIC), 03-04 April 2022, London, United Kingdom}, journal = {16th European Microwave Integrated Circuits Conference (EuMIC), 03-04 April 2022, London, United Kingdom}, doi = {10.23919/EuMIC50153.2022.9783953}, pages = {4}, language = {en} } @misc{SuetbasNgyWesseletal., author = {S{\"u}tbas, Batuhan and Ngy, Herman Jalli and Wessel, Jan and K{\"o}lpin, Alexander and Kahmen, Gerhard}, title = {Low-Power Ka- and V-Band Miller Compensated Amplifiers in 130-nm SiGe BiCMOS Technology}, series = {16th European Microwave Integrated Circuits Conference (EuMIC), 03-04 April 2022, London, United Kingdom}, journal = {16th European Microwave Integrated Circuits Conference (EuMIC), 03-04 April 2022, London, United Kingdom}, isbn = {978-2-87487-064-4}, doi = {10.23919/EuMIC50153.2022.9783785}, pages = {4}, language = {en} } @misc{SuetbasKahmen, author = {S{\"u}tbas, Batuhan and Kahmen, Gerhard}, title = {A 7.2-mW V-Band Frequency Doubler with 14\% Total Efficiency in 130-nm SiGe BiCMOS}, series = {IEEE Microwave and Wireless Components Letters}, volume = {32}, journal = {IEEE Microwave and Wireless Components Letters}, number = {6}, issn = {1531-1309}, doi = {10.1109/LMWC.2022.3141557}, pages = {579 -- 582}, language = {en} } @misc{DziallasFatemiPeczeketal., author = {Dziallas, Giannino and Fatemi, Adel and Peczek, Anna and Zimmermann, Lars and Malignaggi, Andrea and Kahmen, Gerhard}, title = {A 56-Gb/s Optical Receiver with 2.08-µA Noise Monolithically Integrated into a 250-nm SiGe BiCMOS Technology}, series = {IEEE Transactions on Microwave Theory and Techniques}, volume = {70}, journal = {IEEE Transactions on Microwave Theory and Techniques}, number = {1}, issn = {0018-9480}, doi = {10.1109/TMTT.2021.3104838}, pages = {10}, language = {en} } @misc{EissaFischerMausolfetal., author = {Eissa, Mohamed Hussein and Fischer, Gunter and Mausolf, Thomas and R{\"u}cker, Holger and Malignaggi, Andrea and Kahmen, Gerhard}, title = {220-320-GHz J-Band 4-Way Power Amplifier in Advanced 130-nm BiCMOS Technology}, series = {IEEE Microwave and Wireless Components Letters}, volume = {32}, journal = {IEEE Microwave and Wireless Components Letters}, number = {11}, issn = {1531-1309}, doi = {10.1109/LMWC.2022.3181407}, pages = {1335 -- 1338}, language = {en} }