@misc{VierhausJenihhinSonzaReorda, author = {Vierhaus, Heinrich Theodor and Jenihhin, Maksim and Sonza-Reorda, Matteo}, title = {RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality}, series = {2018 Proceedings of the 12th European Workshop on Microelectronics Education (EWME), Braunschweig, 24-26 Sept. 2018}, journal = {2018 Proceedings of the 12th European Workshop on Microelectronics Education (EWME), Braunschweig, 24-26 Sept. 2018}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-5386-9114-4}, doi = {10.1109/EWME.2018.8629465}, pages = {45 -- 50}, language = {en} } @misc{JenihhinHamdiouiSonzaReordaetal., author = {Jenihhin, Maksim and Hamdioui, Said and Sonza-Reorda, Matteo and Krstic, Milos and Langend{\"o}rfer, Peter and Sauer, Christian and Klotz, Anton and H{\"u}bner, Michael and Nolte, J{\"o}rg and Vierhaus, Heinrich Theodor and Selimis, Georgions and Alexandrescu, Dan and Taouil, Mottaqiallah and Schrijen, Geert-Jan and Sterpone, Luca and Squillero, Giovanni and Dyka, Zoya and Raik, Jaan}, title = {RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems}, series = {ArXiv.org}, journal = {ArXiv.org}, pages = {7}, language = {en} } @misc{NazariTaheriAzarpeyvandetal., author = {Nazari, Samira and Taheri, Mahdi and Azarpeyvand, Ali and Afsharchi, Mohsen and Ghasempouri, Tara and Herglotz, Christian and Daneshtalab, Masoud and Jenihhin, Maksim}, title = {FORTUNE : a negative memory overhead hardware-agnostic fault TOleRance techniqUe in DNNs}, series = {2024 IEEE 33rd Asian Test Symposium (ATS)}, journal = {2024 IEEE 33rd Asian Test Symposium (ATS)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, isbn = {979-8-3315-2917-8}, issn = {2377-5386}, doi = {10.1109/ATS64447.2024.10915463}, pages = {1 -- 6}, abstract = {This paper presents FORTUNE, a hardware-agnostic fault tolerance technique for DNNs that leverages quantization to enhance reliability without significant performance overhead. Unlike conventional methods like Triple Modular Redundancy (TMR), which are computationally expensive, the proposed approach uses memory savings from quantization to protect the critical Most Significant Bit, improving fault tolerance in Deep Neural Networks (DNNs). Memory utilization has been reduced by 37.5\% across all networks, with vulnerability in AlexNet reduced by 56\% compared to the 8-bit version and 84\% compared to the unprotected 3-bit version. These improvements come with only a minor increase in execution time of less than 3\%. Using AlexNet as an example demonstrates how our approach effectively enhances memory utilization and resilience while causing only a minimal increase in execution time.}, language = {en} } @misc{NazariTaheriAzarpeyvandetal., author = {Nazari, Samira and Taheri, Mahdi and Azarpeyvand, Ali and Afsharchi, Mohsen and Herglotz, Christian and Jenihhin, Maksim}, title = {Reliability-aware performance optimization of DNN HW accelerators through heterogeneous quantization}, series = {2025 IEEE 26th Latin American Test Symposium (LATS)}, journal = {2025 IEEE 26th Latin American Test Symposium (LATS)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, isbn = {978-1-6654-7763-5}, issn = {2373-0862}, doi = {10.1109/LATS65346.2025.10963948}, pages = {1 -- 6}, abstract = {The paper introduces a framework for implementing heterogeneous quantization tailored to individual layers of DNN accelerators. The proposed method, evaluated across DNN benchmarks AlexNet, VGG-11 and ResNet-18, enhances both accuracy drop and performance. On average, the accuracy drop at a BER of 10-4 was reduced by nearly 4 times compared to homogeneous quantization, demonstrating a considerable improvement in reliability under fault-prone conditions. Furthermore, the memory overhead introduced by the method for protected heterogeneous networks is less than 0.1\%, highlighting that these reliability gains come with negligible resource costs.}, language = {en} } @misc{PappalardoBellarminoDeveautouretal., author = {Pappalardo, Salvatore and Bellarmino, Nicolo' and Deveautour, Bastien and Bosio, Alberto and Taheri, Mahdi and Daneshtalab, Masoud and Raik, Jaan and Jenihhin, Maksim}, title = {SAFFIRA : a framework for assessing the reliability of systolic-array DNN accelerators}, series = {Journal of circuits, systems, and computers : JCSC}, volume = {34}, journal = {Journal of circuits, systems, and computers : JCSC}, number = {18}, publisher = {World Scientific}, address = {Singapore}, issn = {1793-6454}, doi = {https://doi.org/10.1142/S0218126625430017}, abstract = {Systolic array has emerged as a prominent architecture for Deep Neural Network (DNN) hardware accelerators, providing high-throughput and low-latency performance essential for deploying DNNs across diverse applications. However, when used in safety-critical applications, reliability assessment is mandatory to guarantee the correct behavior of DNN accelerators. While fault injection stands out as a well-established practical and robust method for reliability assessment, it is still a very time-consuming process. This paper addresses the time efficiency issue by introducing a novel hierarchical software-based hardware-aware fault injection strategy tailored for systolic array-based DNN accelerators. A Uniform Recurrent Equations system is used for software modeling of the systolic-array core of the DNN accelerators. The approach demonstrates a reduction of the fault injection time up to 3× compared to the state-of-the-art hybrid (software/hardware) hardware-aware fault injection frameworks and more than 2000× compared to RT-level fault injection frameworks without compromising the accuracy from the application level. Additionally, we introduce novel reliability metrics to better evaluate the robustness of a deep neural network system. The performance of the framework is studied on state-of-the-art DNN benchmarks.}, language = {en} } @misc{SharifianTaheriRashtchietal., author = {Sharifian, Saeed and Taheri, Mahdi and Rashtchi, Vahid and Azarpeyvand, Ali and Herglotz, Christian and Jenihhin, Maksim}, title = {Reliability-aware hyperparameter optimization for ANN-to-SNN conversion}, series = {WiPiEC journal : works in progress in embedded computing journal : special issue}, volume = {11}, journal = {WiPiEC journal : works in progress in embedded computing journal : special issue}, number = {1}, publisher = {WiPiEC Journal}, address = {Podgorica, Montenegro}, issn = {2980-7298}, doi = {https://doi.org/10.64552/wipiec.v11i1.85}, pages = {1 -- 7}, abstract = {Spiking Neural Networks (SNNs) have emerged as an energy-efficient alternative to Artificial Neural Networks (ANNs), particularly for edge-computing and safety-critical applications. Unlike conventional ANNs, SNNs leverage sparse event-driven processing to reduce energy consumption while significantly maintaining high computational efficiency. This paper presents a framework designed to optimize the conversion of ANNs into equivalent SNNs while balancing accuracy, reliability, and energy efficiency. The proposed framework systematically explores SNN hyperparameters to identify configurations that achieve superior performance compared to their ANN counterparts. Experimental evaluations on MNIST and Fashion-MNIST datasets with different network topologies demonstrate that the optimized SNNs achieve comparable accuracy while offering in some cases 27.81× and 15.17× lower energy consumption and 1.92× and 1.84× less accuracy drop in the presence of faults, respectively, over the ANN baseline. The results highlight the applicability of SNNs in reliability-critical power-constrained environments.}, language = {en} } @misc{TaheriPatneCherezovaetal., author = {Taheri, Mahdi and Patne, Parth and Cherezova, Natalia and Mahani, Ali and Herglotz, Christian and Jenihhin, Maksim}, title = {RL-agent-based early-exit DNN architecture search framework}, series = {IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) : proceedings}, journal = {IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) : proceedings}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {979-8-3315-2801-0}, issn = {2334-3133}, doi = {10.1109/DDECS63720.2025.11006795}, pages = {145 -- 148}, abstract = {This paper introduces a Reinforcement Learning (RL)-based framework for optimizing early-exit configurations in Deep Neural Networks (DNNs). By integrating RL with BranchyNet-inspired architectures, the framework dynamically determines optimal early exit placements and confidence thresholds, balancing inference time, energy consumption, and accuracy. Key contributions include an early-exit DNN architecture search, an RL-driven threshold optimization process during training, and a design-space exploration open-source framework. Experiments on models such as ResNet-18, VGG-16, and AlexNet, using benchmarks like CIFAR-10 and MNIST, reveal significant reductions in inference time (up to 69.7x) and power consumption while keeping accuracy drop within 1-2\%. This work demonstrates that dynamic early-exit strategies can enhance DNN efficiency while maintaining performance, paving the way for resource-constrained applications.}, language = {en} } @misc{NazariTaheriAzarpeyvandetal., author = {Nazari, Samira and Taheri, Mahdi and Azarpeyvand, Ali and Afsharchi, Mohsen and Herglotz, Christian and Jenihhin, Maksim}, title = {GENIE : GENetIc algorithm-based REliability assessment methodology for deep neural networks}, series = {2025 11th International Conference on Computing and Artificial Intelligence (ICCAI)}, journal = {2025 11th International Conference on Computing and Artificial Intelligence (ICCAI)}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {979-8-3315-2492-0}, doi = {10.1109/ICCAI66501.2025.00049}, pages = {1 -- 8}, abstract = {As deep neural networks (DNNs) are becoming vital to numerous safety-critical applications, ensuring their fault reliability is crucial. This paper presents a hybrid framework that combines genetic algorithms with fault injection and analytical methods to identify vulnerable neurons and layers in DNNs. Validated on LeNet-5, AlexNet, and VGG-11, our approach significantly enhances model accuracy in harsh environments by protecting critical components, achieving reliability improvements (accuracy drop of the model compared to the golden network after fault injection) of 69.86\% for LeNet, and 99.65\% for AlexNet at BER=1E-4, and 91.37\% improvement for VGG at BER=1E-6. Furthermore, our framework reduces computational costs by requiring fewer inferences than traditional analytical methods, highlighting its potential to improve DNN accelerators' reliability and contribute to their safety.}, language = {en} } @misc{HosseiniAzarpeyvandTaherietal., author = {Hosseini, Mostafa and Azarpeyvand, Ali and Taheri, Mahdi and Ghasempouri, Tara and Jenihhin, Maksim}, title = {SHIELD : PSO-based hardware Trojan detection for efficient and low-cost defense}, series = {IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS)}, journal = {IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS)}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {979-8-3315-3334-2}, issn = {1942-9398}, doi = {10.1109/IOLTS65288.2025.11116879}, pages = {1 -- 4}, abstract = {Semiconductor supply chain vulnerability presents a significant obstacle to creating reliable systems. At various phases of the Integrated Circuit (IC) design life-cycle, malicious modifications, known as Hardware Trojans (HTs), can be introduced. Logic testing, a widely recognized approach for Automatic test pattern Generation (ATPG) in HT detection, encounters substantial challenges due to the vast complexity of the search space, making it impractical and leading to inadequate trigger coverage. This paper proposes a Particle Swarm Optimization (PSO) based method that leverages information on effective inputs to facilitate the detection of conditionally triggered ultra-small HTs. An evaluation of the technique on ISCAS-85 benchmarks reveals substantial improvements in trigger coverage and a notable reduction in runtime compared to state-of-the-art methods.}, language = {en} }