@book{VierhausSteiningerPawlaketal., author = {Vierhaus, Heinrich Theodor and Steininger, Andreas and Pawlak, A. and Kraemer, Rolf and Sch{\"o}lzel, Mario and Raik, Jaan}, title = {Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems}, publisher = {Piscataway : IEEE, 2011}, isbn = {978-1-4244-9753-9}, language = {en} } @misc{JenihhinHamdiouiSonzaReordaetal., author = {Jenihhin, Maksim and Hamdioui, Said and Sonza-Reorda, Matteo and Krstic, Milos and Langend{\"o}rfer, Peter and Sauer, Christian and Klotz, Anton and H{\"u}bner, Michael and Nolte, J{\"o}rg and Vierhaus, Heinrich Theodor and Selimis, Georgions and Alexandrescu, Dan and Taouil, Mottaqiallah and Schrijen, Geert-Jan and Sterpone, Luca and Squillero, Giovanni and Dyka, Zoya and Raik, Jaan}, title = {RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems}, series = {ArXiv.org}, journal = {ArXiv.org}, pages = {7}, language = {en} } @misc{AzadNiazmandJansonetal., author = {Azad, Siavoosh Payandeh and Niazmand, Behrad and Janson, Karl and George, Nevin and Oyeniran, Stephen Adeboye and Putkaradze, Tsotne and Kaur, Apneet and Raik, Jaan and Jervan, Gert and Ubar, Raimund and Hollstein, Thomas}, title = {From online fault detection to fault management in Network-on-Chips: A ground-up approach}, series = {IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems (DDECS), Dresden, Germany, 19-21 April 2017}, journal = {IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems (DDECS), Dresden, Germany, 19-21 April 2017}, isbn = {978-1-5386-0472-4}, issn = {2473-2117}, doi = {10.1109/DDECS.2017.7934565}, language = {en} } @misc{PappalardoBellarminoDeveautouretal., author = {Pappalardo, Salvatore and Bellarmino, Nicolo' and Deveautour, Bastien and Bosio, Alberto and Taheri, Mahdi and Daneshtalab, Masoud and Raik, Jaan and Jenihhin, Maksim}, title = {SAFFIRA : a framework for assessing the reliability of systolic-array DNN accelerators}, series = {Journal of circuits, systems, and computers : JCSC}, volume = {34}, journal = {Journal of circuits, systems, and computers : JCSC}, number = {18}, publisher = {World Scientific}, address = {Singapore}, issn = {1793-6454}, doi = {https://doi.org/10.1142/S0218126625430017}, abstract = {Systolic array has emerged as a prominent architecture for Deep Neural Network (DNN) hardware accelerators, providing high-throughput and low-latency performance essential for deploying DNNs across diverse applications. However, when used in safety-critical applications, reliability assessment is mandatory to guarantee the correct behavior of DNN accelerators. While fault injection stands out as a well-established practical and robust method for reliability assessment, it is still a very time-consuming process. This paper addresses the time efficiency issue by introducing a novel hierarchical software-based hardware-aware fault injection strategy tailored for systolic array-based DNN accelerators. A Uniform Recurrent Equations system is used for software modeling of the systolic-array core of the DNN accelerators. The approach demonstrates a reduction of the fault injection time up to 3× compared to the state-of-the-art hybrid (software/hardware) hardware-aware fault injection frameworks and more than 2000× compared to RT-level fault injection frameworks without compromising the accuracy from the application level. Additionally, we introduce novel reliability metrics to better evaluate the robustness of a deep neural network system. The performance of the framework is studied on state-of-the-art DNN benchmarks.}, language = {en} }