@misc{LohsSiegemundNolteetal., author = {Lohs, Stefan and Siegemund, Gerry and Nolte, J{\"o}rg and Turau, Volker}, title = {Influence of Topology-Fluctuations on Self-Stabilizing Algorithms}, series = {International Conference on Distributed Computing in Sensor Systems (DCOSS)}, journal = {International Conference on Distributed Computing in Sensor Systems (DCOSS)}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-5090-1460-6}, pages = {122 -- 124}, abstract = {Self-stabilizing systems have in theory the unique and provable ability, to always return to a valid system state even in the face of failures. These properties are certainly desirable for domains like wireless ad-hoc networks with numerous unpredictable faults. Unfortunately, the time in which the system returns to a valid state is not predictable and potentially unbound. The failure rate typically depends on physical phenomena and in self-stabilizing systems each node tries to react to failures in an inherently adaptive fashion by the cyclic observation of the states of its neighbors. When state changes are either too quick or too slow the system might never reach a state that is sufficiently stable for a specific task. In this paper, we investigate the influences of the error rate on the (stability) convergence time on the basis of topology information acquired in real network experiments. This allows us to asses the asymptotic behavior of relevant self-stabilizing algorithms in typical wireless networks.}, language = {en} } @misc{BuechnerLopacinskiNolteetal., author = {B{\"u}chner, Steffen and Lopacinski, Lukasz and Nolte, J{\"o}rg and Kraemer, Rolf}, title = {100 Gbit/s End-to-End Communication: Designing Scalable Protocols with Soft Real-Time Stream Processing}, series = {2016 IEEE 41st Conference on Local Computer Networks, 7-10 Nov. 2016}, journal = {2016 IEEE 41st Conference on Local Computer Networks, 7-10 Nov. 2016}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-5090-2054-6}, doi = {10.1109/LCN.2016.25}, language = {en} } @misc{RottaNolteNikolovetal., author = {Rotta, Randolf and Nolte, J{\"o}rg and Nikolov, Vladimir and Schubert, Lutz and Bonfert, Stefan and Wesner, Stefan}, title = {MyThOS — Scalable OS Design for Extremely Parallel Applications}, series = {2016 Intl IEEE Conferences on Ubiquitous Intelligence Computing, Advanced and Trusted Computing, Scalable Computing and Communications, Cloud and Big Data Computing, Internet of People, and Smart World Congress, 18-21 July 2016}, journal = {2016 Intl IEEE Conferences on Ubiquitous Intelligence Computing, Advanced and Trusted Computing, Scalable Computing and Communications, Cloud and Big Data Computing, Internet of People, and Smart World Congress, 18-21 July 2016}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-5090-2771-2}, doi = {10.1109/UIC-ATC-ScalCom-CBDCom-IoP-SmartWorld.2016.0179}, pages = {1165 -- 1172}, abstract = {Many-core architectures trade single-thread performance for a larger number of cores. Scalable throughput can be attained only by a high degree of parallelism, minimized synchronization. Whilst this is achievable for many applications, the operating system still introduces bottlenecks through non-local sharing, synchronization,, message passing. A particular challenge for highly dynamic applications, for example invasive HPC applications, elastic compute clouds, is the management of short-living application threads, processes. This paper discusses OS architecture choices based on microkernel, multikernel, distributed systems designs, our development experience in the context of the MyThOS project. Initial experiments show a much faster thread creation, activation compared to monolithic systems like Linux while providing a more flexible protection, threading model that is better suited for dynamic scenarios. However, despite significant progress in the overall domain of operating systems, the design space for scalable many-core operating systems is yet to be fully explored.}, language = {en} } @misc{RottaKubanSchoepsetal., author = {Rotta, Randolf and Kuban, Robert and Sch{\"o}ps, Mark Simon and Nolte, J{\"o}rg}, title = {Dealing with Layers of Obfuscation in pseudo-Uniform Memory Architectures}, series = {Euro-Par 2016: Parallel Processing Workshops, Euro-Par 2016 International Workshops, Grenoble, France, August 24-26, 2016}, journal = {Euro-Par 2016: Parallel Processing Workshops, Euro-Par 2016 International Workshops, Grenoble, France, August 24-26, 2016}, publisher = {Springer International Publishing}, address = {Cham}, isbn = {978-3-319-58942-8}, doi = {10.1007/978-3-319-58943-5_55}, pages = {685 -- 696}, abstract = {Pseudo-Uniform Memory Architectures hide the memory's throughput bottlenecks and the network's latency differences in order to provide near-peak average throughput for computations on large datasets. This obviates the need for application-level partitioning and load balancing between NUMA domains but the performance of cross-core communication still depends on the actual placement of the involved variables and cores, which can result in significant variation within applications and between application runs. This paper analyses the pseudo-uniform memory latency on the Intel Xeon Phi Knights Corner processor, derives strategies for the optimised placement of important variables, and discusses the role of localised coordination in pUMA systems. For example, a basic cache line ping-pong benchmark showed a 3x speedup between adjacent cores. Therefore, pUMA systems combined with support for controlled placement of small datasets are an interesting option when processor-wide load balancing is difficult while localised coordination is feasible.}, language = {en} } @misc{LopacinskiBrzozowskiKraemeretal., author = {Lopacinski, Lukasz and Brzozowski, Marcin and Kraemer, Rolf and B{\"u}chner, Steffen and Nolte, J{\"o}rg}, title = {Improving Energy Efficiency using a Link Adaptation Algorithm Dedicated for 100 Gbps Wireless Communication}, series = {AE{\"U} - International Journal of Electronics and Communications}, volume = {81}, journal = {AE{\"U} - International Journal of Electronics and Communications}, issn = {1434-8411}, pages = {67 -- 73}, language = {en} } @inproceedings{LopacinskiBrzozowskiKraemeretal., author = {Lopacinski, Lukasz and Brzozowski, Marcin and Kraemer, Rolf and KrishneGowda, Karthik and B{\"u}chner, Steffen and Nolte, J{\"o}rg}, title = {Towards 100 Gbps Wireless Communication: Investigation of FEC Interleavers for PSSS-15 Spreading}, series = {IEEE EUROCON 2017, 17th International Conference on Smart Technologies, Ohrid, Macedonia, 6-8 July 2017}, booktitle = {IEEE EUROCON 2017, 17th International Conference on Smart Technologies, Ohrid, Macedonia, 6-8 July 2017}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-5090-3843-5}, pages = {619 -- 623}, language = {en} } @misc{BuechnerLopacinskiKraemeretal., author = {B{\"u}chner, Steffen and Lopacinski, Lukasz and Kraemer, Rolf and Nolte, J{\"o}rg}, title = {Protocol Processing for 100 Gbit/s and Beyond - A Soft Real-Time Approach in Hardware and Software}, series = {Frequenz: Journal of RF-Engineering and Telecommunications}, volume = {71}, journal = {Frequenz: Journal of RF-Engineering and Telecommunications}, number = {9-10}, issn = {2191-6349}, pages = {427 -- 438}, language = {en} } @misc{BuechnerNolteHasanietal., author = {B{\"u}chner, Steffen and Nolte, J{\"o}rg and Hasani, Alireza and Kraemer, Rolf}, title = {100 Gbit/s End-to-End Communication: Low Overhead On-Demand Protocol Replacement in High Data Rate Communication Systems}, series = {42nd Conference on Local Computer Networks (LCN), 9-12 Oct. 2017, Singapore}, journal = {42nd Conference on Local Computer Networks (LCN), 9-12 Oct. 2017, Singapore}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-5090-6523-3}, doi = {10.1109/LCN.2017.40}, pages = {231 -- 234}, language = {en} } @misc{KarnapkeNolte, author = {Karnapke, Reinhardt and Nolte, J{\"o}rg}, title = {Unidirectional Link Counter - a Routing Protocol for Wireless Sensor Networks with Many Unidirectional Links}, series = {14th Annual Mediterranean Ad Hoc Networking Workshop (Med-Hoc-Net 2015), Vilamoura, Portugal, 17 - 18 June 2015}, journal = {14th Annual Mediterranean Ad Hoc Networking Workshop (Med-Hoc-Net 2015), Vilamoura, Portugal, 17 - 18 June 2015}, publisher = {IEEE}, address = {Piscataway}, isbn = {978-1-4673-7306-7}, pages = {1 -- 7}, language = {en} } @misc{KubanRottaNolte, author = {Kuban, Robert and Rotta, Randolf and Nolte, J{\"o}rg}, title = {Help Your Busy Neighbors: Dynamic Multicasts over Static Topologies}, series = {Euro-Par 2017: Parallel Processing Workshops}, journal = {Euro-Par 2017: Parallel Processing Workshops}, editor = {Heras, Dora B. and Boug{\´e}, Luc}, publisher = {Springer}, address = {Cham}, isbn = {978-3-319-75177-1}, doi = {10.1007/978-3-319-75178-8_51}, pages = {636 -- 657}, language = {en} } @misc{SegabinazziFerreiraNolte, author = {Segabinazzi Ferreira, Raphael and Nolte, J{\"o}rg}, title = {Low latency reconfiguration mechanism for fine-grained processor internal functional units}, series = {2019 IEEE Latin American Test Symposium (LATS)}, journal = {2019 IEEE Latin American Test Symposium (LATS)}, isbn = {978-1-7281-1756-0}, issn = {2373-0862}, doi = {10.1109/LATW.2019.8704560}, pages = {6}, abstract = {The strive for performance, low power consumption, and less chip area have been diminishing the reliability and the time to fault occurrences due to wear out of electronic devices. Recent research has shown that functional units within processors usually execute a different amount of operations when running programs. Therefore, these units present different individual wear out during their lifetime. Most existent schemes for reconfiguration of processors due to fault detection and other processor parameters are done at the level of cores which is a costly way to achieve redundancy. This paper presents a low latency (approximately 1 clock cycle) software controlled mechanism to reconfigure units within processor cores according to predefined parameters. Such reconfiguration capability delivers features like wear out balance of processor functional units, configuration of units according to the criticality of tasks running on an operating system and configurations to gain in performance (e.g. parallel execution) when possible. The focus of this paper is to show the implemented low latency reconfiguration mechanism and highlight its possible main features.}, language = {en} } @misc{SegabinazziFerreiraGeorgeChenetal., author = {Segabinazzi Ferreira, Raphael and George, Nevin and Chen, Junchao and H{\"u}bner, Michael and Krstic, Milos and Nolte, J{\"o}rg and Vierhaus, Heinrich Theodor}, title = {Configurable Fault Tolerant Circuits and System Level Integration for Self-Awareness}, series = {Proceedings of the Work in Progress Session held in connection with SEAA 2019, the 45th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2019, the 22nd EUROMICRO Conference on Digital System Design}, journal = {Proceedings of the Work in Progress Session held in connection with SEAA 2019, the 45th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2019, the 22nd EUROMICRO Conference on Digital System Design}, publisher = {SEA-Publications}, address = {Kallithea, Chalkidiki (Greece)}, isbn = {978-3-902457-54-7}, doi = {10.26127/BTUOpen-5050}, pages = {2}, abstract = {Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on- line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system.}, language = {en} } @misc{JenihhinHamdiouiSonzaReordaetal., author = {Jenihhin, Maksim and Hamdioui, Said and Sonza-Reorda, Matteo and Krstic, Milos and Langend{\"o}rfer, Peter and Sauer, Christian and Klotz, Anton and H{\"u}bner, Michael and Nolte, J{\"o}rg and Vierhaus, Heinrich Theodor and Selimis, Georgions and Alexandrescu, Dan and Taouil, Mottaqiallah and Schrijen, Geert-Jan and Sterpone, Luca and Squillero, Giovanni and Dyka, Zoya and Raik, Jaan}, title = {RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems}, series = {ArXiv.org}, journal = {ArXiv.org}, pages = {7}, language = {en} } @misc{SegabinazziFerreiraNolteVargasetal., author = {Segabinazzi Ferreira, Raphael and Nolte, J{\"o}rg and Vargas, Fabian and George, Nevin and H{\"u}bner, Michael}, title = {Run-time Hardware Reconfiguration of Functional Units to Support Mixed-Critical Applications}, series = {IEEE Latin American Test Symposium (LATS), Macei{\´o}, Brazil}, journal = {IEEE Latin American Test Symposium (LATS), Macei{\´o}, Brazil}, doi = {10.1109/LATS49555.2020.9093692}, pages = {6}, language = {en} } @misc{HasaniLopacinskiBuechneretal., author = {Hasani, Alireza and Lopacinski, Lukasz and B{\"u}chner, Steffen and Nolte, J{\"o}rg and Kraemer, Rolf}, title = {A Modified Shuffling Method to Split the Critical Path Delay in Layered Decoding of QC-LDPC Codes}, series = {30th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC 2019), Istanbul, Turkey, 08 - 11 September 2019}, journal = {30th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC 2019), Istanbul, Turkey, 08 - 11 September 2019}, isbn = {978-1-5386-8110-7}, issn = {2166-9589}, doi = {10.1109/PIMRC.2019.8904435}, language = {en} }