@misc{BrandaleroVeleskiMunozHernandezetal., author = {Brandalero, Marcelo and Veleski, Mitko and Mu{\~n}oz-Hernandez, Hector Gerardo and Ali, Muhammad and Le Jeune, Laurens and Goedem{\´e}, Toon and Mentens, Nele and Vandendriessche, Jurgen and Lhoest, Lancelot and Da Silva, Bruno A. and Touhafi, Abdellah and Goehringer, Diana and H{\"u}bner, Michael}, title = {Embedded AI Techniques for Industrial Applications}, series = {31st International Conference on Field-Programmable Logic and Applications (FPL), Dresden, Germany, 30 August-3 September 2021}, journal = {31st International Conference on Field-Programmable Logic and Applications (FPL), Dresden, Germany, 30 August-3 September 2021}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-6654-3759-2}, doi = {10.1109/FPL53798.2021.00071}, pages = {374 -- 375}, language = {en} } @misc{BrandaleroAliLeJeuneetal., author = {Brandalero, Marcelo and Ali, Muhammad and Le Jeune, Laurens and Munoz-Hernandez, Hector Gerardo and Veleski, Mitko and Silva, Bruno da and Lemeire, Jan and Van Beeck, Kristof and Touhafi, Abdellah and Goedem{\´e}, Toon and Mentens, Nele and G{\"o}hringer, Diana and H{\"u}bner, Michael}, title = {AITIA: Embedded AI Techniques for Industrial Applications}, series = {International Conference on Omni-Layer Intelligent Systems (COINS), 31 August-2 September 2020, Barcelona, Spain}, journal = {International Conference on Omni-Layer Intelligent Systems (COINS), 31 August-2 September 2020, Barcelona, Spain}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-7281-6371-0}, doi = {10.1109/COINS49042.2020.9191672}, pages = {1 -- 7}, language = {en} } @misc{MunozHernandezAliShahinetal., author = {Mu{\~n}oz-Hernandez, Hector Gerardo and Ali, Muhammad and Shahin, Keyvan and Siyavashi, Alireza and G{\"o}hringer, Diana and Reichenbach, Marc and Herglotz, Christian and H{\"u}bner, Michael}, title = {Towards complete open-source environments : FPGA-based GPU overlay controlled by RISC-V}, series = {Architecture of computing systems : 38th International Conference, ARCS 2025 Kiel, Germany, April 22-24, 2025, proceedings}, journal = {Architecture of computing systems : 38th International Conference, ARCS 2025 Kiel, Germany, April 22-24, 2025, proceedings}, publisher = {Springer}, address = {Berlin}, isbn = {978-3-032-03280-5}, issn = {0302-9743}, doi = {https://doi.org/10.1007/978-3-032-03281-2_7}, pages = {94 -- 108}, abstract = {Image and signal processing applications have been widely implemented in Field Programmable Gate Arrays (FPGAs) and Graphical Processing Units (GPUs) due to their energy efficiency and performance, respectively. GPUs provide high data processing parallelism and are usually chosen to accelerate applications where low energy consumption is not a high priority. On the other hand, FPGAs are more tailored to hardware solutions due to their reconfigurability, but they struggle to outperform GPUs in data throughput. Soft IP cores implemented on reconfigurable hardware, are an alternative offering advantages from both worlds. Some of these soft-core solutions offer an entire environment that includes scripts to automate their implementation, custom compilers, and other diverse tools. Unfortunately, some of these soft-cores are dependent on proprietary Intellectual Property (IP) or require hardware expertise to use properly. In this work, we propose an extended version of a popular open-source soft GPU, which can now run alongside a soft RISC-V core, and with High-Bandwidth memory (HBM2) compatibility. Previously, this soft GPU was only ready to be deployed in boards with a hard ARM core, but now it can be easily used in FPGAs without this requirement. We also provide an evaluation of how the soft GPU performs with respect to the pure RISC-V core, and a hard ARM core achieving geometric mean speed-ups of 114.60x and 19.72x respectively when performing some image and signal processing applications. Finally, we demonstrate how our soft GPU benefits from the HBM integration.}, language = {en} }