@misc{BielefeldtBasenerKhanetal., author = {Bielefeldt, Jens and Basener, Kai-Uwe and Khan, Siddique R. and Massah, Mozhdeh and Wiesbrock, Hans-Werner and Scharoba, Stefan and H{\"u}bner, Michael}, title = {Einsatz von Deep Learning f{\"u}r den Test Eingebetteter Systeme }, series = {Informatik 2021: computer science \& sustainability, 27. September-01. Oktober 2021, Berlin}, journal = {Informatik 2021: computer science \& sustainability, 27. September-01. Oktober 2021, Berlin}, publisher = {Gesellschaft f{\"u}r Informatik e.V.}, address = {Bonn}, isbn = {978-3-88579-708-1}, doi = {10.18420/INFORMATIK2021-166}, language = {de} } @misc{MahmoodScharobaSchorlemeretal., author = {Mahmood, Safdar and Scharoba, Stefan and Schorlemer, Jonas and Schulz, Christian and H{\"u}bner, Michael and Reichenbach, Marc}, title = {Detecting Improvised Land-mines using Deep Neural Networks on GPR Image Dataset targeting FPGAs }, series = {IEEE Nordic Circuits and Systems Conference (NORCAS), 25-26 October 2022, Oslo, Norway}, journal = {IEEE Nordic Circuits and Systems Conference (NORCAS), 25-26 October 2022, Oslo, Norway}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {979-8-3503-4550-6}, doi = {10.1109/norcas57515.2022.9934735}, pages = {1 -- 7}, language = {en} } @misc{MahmoodHuebnerReichenbach, author = {Mahmood, Safdar and H{\"u}bner, Michael and Reichenbach, Marc}, title = {A Design-Space Exploration Framework for Application-Specific Machine Learning Targeting Reconfigurable Computing}, series = {Applied Reconfigurable Computing. Architectures, Tools, and Applications, 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023}, journal = {Applied Reconfigurable Computing. Architectures, Tools, and Applications, 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023}, editor = {Palumbo, Francesca and Keramidas, Georgios and Voros, Nikolaos and Diniz, Pedro C.}, publisher = {Springer}, address = {Cham}, isbn = {978-3-031-42921-7}, doi = {10.1007/978-3-031-42921-7_27}, pages = {371 -- 374}, language = {en} } @misc{DaSilvaCardosoNardoetal., author = {Da Silva, Samuel Souza and Cardoso, Matheus and Nardo, Lucas and Nepomuceno, Erivelton and H{\"u}bner, Michael and Arias-Garcia, Janier}, title = {A New Chaos-Based PRNG Hardware Architecture Using The HUB Fixed-Point Format}, series = {IEEE Transactions on Instrumentation and Measurement}, volume = {Vol. 72}, journal = {IEEE Transactions on Instrumentation and Measurement}, issn = {1557-9662}, doi = {10.1109/TIM.2023.3235457}, pages = {1 -- 8}, language = {en} } @misc{ShahinHuebnerHerglotz, author = {Shahin, Keyvan and H{\"u}bner, Michael and Herglotz, Christian}, title = {A width-configurable hardware approach for accelerating fixed-point simulation}, series = {IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, journal = {IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {979-8-3315-3477-6}, issn = {2159-3477}, doi = {10.1109/ISVLSI65124.2025.11130205}, pages = {6}, abstract = {Fixed-point simulation is a critical step in the design flow of Digital Signal Processing (DSP) systems and consumes a significant portion of the overall development time. This work proposes a novel hardware-based approach to improve the performance of fixed-point simulation through a widthconfigurable architecture implemented on Field-Programmable Gate Arrays (FPGAs). To our knowledge, this is the first reported hardware-based solution for fixed-point simulation reported in the literature, which provides substantial speedup compared to traditional software-based approaches. The presented approach utilizes High-Level Synthesis (HLS) tools to create modular, reusable components that enhance the design reusability. This approach accelerates fixed-point simulation for various applications, requiring only minor modifications to the application code to utilize it. By incorporating simulation capabilities within reusable functions, this work improves the efficiency and adaptability of the fixed-point simulation process. Implementation results for two FIR filter applications show that the proposed methodology is superior to traditional software-based approaches in reducing simulation time by two orders of magnitude and thus has the potential to improve the productivity of the DSP system design flow.}, language = {en} } @misc{ShahinHuebner, author = {Shahin, Keyvan and H{\"u}bner, Michael}, title = {Accelerating fixed-point simulations using width reconfigurable hardware architectures}, series = {31st International Conference on Field-Programmable Logic and Applications (FPL), Dresden, Germany, 30 August-3 September 2021}, journal = {31st International Conference on Field-Programmable Logic and Applications (FPL), Dresden, Germany, 30 August-3 September 2021}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-6654-3759-2}, issn = {1946-1488}, doi = {10.1109/FPL53798.2021.00055}, pages = {275 -- 276}, abstract = {Digital Signal Processing (DSP) systems can be described using either fixed-point or floating-point for their numeric representations. As the general computers use floating-point representation, software-based simulation tools used for modeling and simulation of the arithmetic operations in DSP systems, use floating-point representation as well. However, synthesizing customized hardware for fixed-point arithmetic operations for FPGAs or ASICs is more efficient compared to their floating-point counterparts. Thus it is necessary to convert the representation of a floating-point simulated algorithm on MATLAB for example, to a fixed-point representation which is more suitable for hardware implementation. While former approaches for this conversion step have always been software-based, like on MATLAB itself, this paper presents a new approach to show the possibility of accelerating it by using hardware width reconfigurable designs.}, language = {en} }