@misc{MiloAnzaloneZambellietal., author = {Milo, Valerio and Anzalone, Francesco and Zambelli, Cristian and Perez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Ossorio, {\´O}scar G. and Olivo, Piero and Wenger, Christian and Ielmini, Daniele}, title = {Optimized programming algorithms for multilevel RRAM in hardware neural networks}, series = {IEEE International Reliability Physics Symposium (IRPS), 2021}, journal = {IEEE International Reliability Physics Symposium (IRPS), 2021}, isbn = {978-1-7281-6894-4}, issn = {1938-1891}, doi = {10.1109/IRPS46558.2021.9405119}, abstract = {A key requirement for RRAM in neural network accelerators with a large number of synaptic parameters is the multilevel programming. This is hindered by resistance imprecision due to cycle-to-cycle and device-to-device variations. Here, we compare two multilevel programming algorithms to minimize resistance variations in a 4-kbit array of HfO 2 RRAM. We show that gate-based algorithms have the highest reliability. The optimized scheme is used to implement a neural network with 9-level weights, achieving 91.5\% (vs. software 93.27\%) in MNIST recognition.}, language = {en} }