@misc{MaldonadoBaroniAldanaetal., author = {Maldonado, David and Baroni, Andrea and Aldana, Samuel and Dorai Swamy Reddy, Keerthi and Pechmann, Stefan and Wenger, Christian and Rold{\´a}n, Juan Bautista and P{\´e}rez, Eduardo}, title = {Kinetic Monte Carlo simulation analysis of the conductance drift in Multilevel HfO2-based RRAM devices}, series = {Nanoscale}, volume = {16}, journal = {Nanoscale}, number = {40}, publisher = {Royal Society of Chemistry (RSC)}, issn = {2040-3364}, doi = {10.1039/d4nr02975e}, pages = {19021 -- 19033}, abstract = {The drift characteristics of valence change memory (VCM) devices have been analyzed through both experimental analysis and 3D kinetic Monte Carlo (kMC) simulations.}, language = {en} } @misc{PetrykDykaPerezetal., author = {Petryk, Dmytro and Dyka, Zoya and P{\´e}rez, Eduardo and Kabin, Ievgen and Katzer, Jens and Sch{\"a}ffner, Jan and Langend{\"o}rfer, Peter}, title = {Sensitivity of HfO2-based RRAM Cells to Laser Irradiation}, series = {Microprocessors and Microsystems}, journal = {Microprocessors and Microsystems}, number = {87}, issn = {0141-9331}, doi = {10.1016/j.micpro.2021.104376}, language = {en} } @misc{WenVargasZhuetal., author = {Wen, Jianan and Vargas, Fabian Luis and Zhu, Fukun and Reiser, Daniel and Baroni, Andrea and Fritscher, Markus and Perez, Eduardo and Reichenbach, Marc and Wenger, Christian and Krstic, Milos}, title = {RRAMulator : an efficient FPGA-based emulator for RRAM crossbar with device variability and energy consumption evaluation}, series = {Microelectronics Reliability}, volume = {168}, journal = {Microelectronics Reliability}, publisher = {Elsevier BV}, address = {Amsterdam}, issn = {0026-2714}, doi = {10.1016/j.microrel.2025.115630}, pages = {1 -- 10}, abstract = {The in-memory computing (IMC) systems based on emerging technologies have gained significant attention due to their potential to enhance performance and energy efficiency by minimizing data movement between memory and processing unit, which is especially beneficial for data-intensive applications. Designing and evaluating systems utilizing emerging memory technologies, such as resistive RAM (RRAM), poses considerable challenges due to the limited support from electronics design automation (EDA) tools for rapid development and design space exploration. Additionally, incorporating technology-dependent variability into system-level simulations is critical to accurately assess the impact on system reliability and performance. To bridge this gap, we propose RRAMulator, a field-programmable gate array (FPGA) based hardware emulator for RRAM crossbar array. To avoid the complex device models capturing the nonlinear current-voltage (IV) relationships that degrade emulation speed and increase hardware utilization, we propose a device and variability modeling approach based on device measurements. We deploy look-up tables (LUTs) for device modeling and use the multivariate kernel density estimation (KDE) method to augment existing data, extending data variety and avoiding repetitive data usage. The proposed emulator achieves cycle-accurate, real-time emulations and provides information such as latency and energy consumption for matrix mapping and vector-matrix multiplications (VMMs). Experimental results show a significant reduction in emulation time compared to conventional behavioral simulations. Additionally, an RRAM-based discrete Fourier transform (DFT) accelerator is analyzed as a case study featuring a range of in-depth system assessments.}, language = {en} } @misc{UhlmannKrysikWenetal., author = {Uhlmann, Max and Krysik, Milosz and Wen, Jianan and Frohberg, Max and Baroni, Andrea and Reddy, Keerthi Dorai Swamy and P{\´e}rez, Eduardo and Ostrovskyy, Philip and Piotrowski, Krzysztof and Carta, Corrado and Wenger, Christian and Kahmen, Gerhard}, title = {A compact one-transistor-multiple-RRAM characterization platform}, series = {IEEE transactions on circuits and systems I : regular papers}, journal = {IEEE transactions on circuits and systems I : regular papers}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {1549-8328}, doi = {10.1109/TCSI.2025.3555234}, pages = {1 -- 12}, abstract = {Emerging non-volatile memories (eNVMs) such as resistive random-access memory (RRAM) offer an alternative solution compared to standard CMOS technologies for implementation of in-memory computing (IMC) units used in artificial neural network (ANN) applications. Existing measurement equipment for device characterisation and programming of such eNVMs are usually bulky and expensive. In this work, we present a compact size characterization platform for RRAM devices, including a custom programming unit IC that occupies less than 1 mm2 of silicon area. Our platform is capable of testing one-transistor-one-RRAM (1T1R) as well as one-transistor-multiple-RRAM (1TNR) cells. Thus, to the best knowledge of the authors, this is the first demonstration of an integrated programming interface for 1TNR cells. The 1T2R IMC cells were fabricated in the IHP's 130 nm BiCMOS technology and, in combination with other parts of the platform, are able to provide more synaptic weight resolution for ANN model applications while simultaneously decreasing the energy consumption by 50 \%. The platform can generate programming voltage pulses with a 3.3 mV accuracy. Using the incremental step pulse with verify algorithm (ISPVA) we achieve 5 non-overlapping resistive states per 1T1R device. Based on those 1T1R base states we measure 15 resulting state combinations in the 1T2R cells.}, language = {en} } @misc{BaroniPerezReddyetal., author = {Baroni, Andrea and P{\´e}rez, Eduardo and Reddy, Keerthi Dorai Swamy and Pechmann, Stefan and Wenger, Christian and Ielmini, Daniele and Zambelli, Cristian}, title = {Enhancing RRAM reliability : exploring the effects of Al doping on HfO2-based devices}, series = {IEEE transactions on device and materials reliability}, journal = {IEEE transactions on device and materials reliability}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {1530-4388}, doi = {10.1109/TDMR.2025.3581061}, pages = {1 -- 9}, abstract = {This study provides a comprehensive evaluation of RRAM devices based on HfO2 and Al-doped HfO2 insulators, focusing on critical performance metrics, including Forming yield, Post-Programming Stability (PPS), Fast Drift, Endurance, and Retention at elevated temperatures (125 ∘C). Aluminum doping significantly enhances device reliability and stability, improving Forming yield, reducing current drift during programming and Retention tests, and minimizing variability during Endurance cycling. While Al5\%:HfO2 achieves most of the observed benefits compared to pure HfO2, Al7\%:HfO2 offers incremental advantages for scenarios requiring extreme reliability. These findings position Al-doped HfO2 devices as a promising solution for RRAM-based systems in memory and neuromorphic computing, highlighting the potential trade-off between performance gains and increased fabrication complexity. This work underlines the importance of material engineering for optimizing RRAM devices in application-specific contexts.}, language = {en} } @misc{BlumensteinPerezWengeretal., author = {Blumenstein, Alan and P{\´e}rez, Eduardo and Wenger, Christian and Dersch, Nadine and Kloes, Alexander and I{\~n}{\´i}guez, Benjam{\´i}n and Schwarz, Mike}, title = {Evaluating device variability in RRAM-based single- and multi-layer perceptrons}, series = {2025 32nd International Conference on Mixed Design of Integrated Circuits and System (MIXDES)}, journal = {2025 32nd International Conference on Mixed Design of Integrated Circuits and System (MIXDES)}, publisher = {IEEE}, address = {New York}, isbn = {978-83-63578-27-5}, doi = {10.23919/MIXDES66264.2025.11092102}, pages = {74 -- 77}, abstract = {This work investigates the impact of stochastic weight variations in hardware implementations of artificial neural networks, focusing on a Single-Layer Perceptron and Multi-Layer Perceptrons. A variable neural network model is introduced, applying Gaussian variability to synaptic weights based on an adjustment rate, which controls the proportion of affected weights. By studying how stochastic variations affect accuracy, simulations under device-to-device and cycle-to-cycle variation conditions demonstrate that Single-Layer Perceptrons are more sensitive to weight variations, while Multi-Layer perceptrons show greater robustness. Additionally, stochastic quantization improves the performance of Multi-Layer Perceptrons but has minimal effect on Single-Layer Perceptrons.}, language = {en} } @misc{WenBaroniUhlmannetal., author = {Wen, Jianan and Baroni, Andrea and Uhlmann, Max and Perez, Eduardo and Wenger, Christian and Krstic, Milos}, title = {ReFFT : an energy-efficient RRAM-based FFT accelerator}, series = {IEEE transactions on computer-aided design of integrated circuits and systems}, journal = {IEEE transactions on computer-aided design of integrated circuits and systems}, publisher = {IEEE}, address = {Piscataway, NJ}, issn = {0278-0070}, doi = {10.1109/TCAD.2025.3627146}, pages = {1 -- 14}, abstract = {The fast Fourier transform (FFT) is a highly efficient algorithm for computing the discrete Fourier transform (DFT). It is widely employed in various applications, including digital communication, image processing, and signal analysis. Recently, in-memory computing architectures based on emerging technologies, such as resistive RAM (RRAM), have demonstrated promising performance with low hardware cost for data-intensive applications. However, directly mapping FFT onto RRAM crossbars is challenging because the algorithm relies on many small, sequential butterfly operations, while cross-bars are optimized for large-scale, highly parallel vector-matrix multiplications (VMMs). In this paper, we introduce ReFFT, a system architecture that reformulates FFT computations for efficient execution on RRAM crossbars. ReFFT combines the reduced computational complexity of FFT with the parallel VMM capability of RRAM. We incorporate measured device data into our framework to analyze the effect of variability and develop an adaptive mapping scheme that improves twiddle-factor programming accuracy, leading to a 9.9 dB peak signal-to-noise ratio (PSNR) improvement for a 256-point FFT. Compared with prior RRAM-based DFT designs, ReFFT achieves up to 4.6× and 19.5× higher energy efficiency for 256- and 2048-point FFTs, respectively. The system is further validated in digital communication and satellite image compression tasks.}, language = {en} } @misc{DerschPerezWengeretal., author = {Dersch, Nadine and Perez, Eduardo and Wenger, Christian and Lanza, Mario and Zhu, Kaichen and Schwarz, Mike and I{\~n}{\´i}guez, Benjam{\´i}n and Kloes, Alexander}, title = {Statistical model for the calculation of conductance variations of memristive devices}, series = {2025 IEEE European Solid-State Electronics Research Conference (ESSERC)}, journal = {2025 IEEE European Solid-State Electronics Research Conference (ESSERC)}, publisher = {IEEE}, address = {Piscataway, NJ}, doi = {10.1109/ESSERC66193.2025.11213973}, pages = {373 -- 376}, abstract = {This paper presents a statistical model which calculates the expected conductance variations from device to device or from cycle to cycle of memristive devices. The mean readout current and its standard deviation can be calculated for binary and multi-level devices. These values are important for simulating hardware-based artificial neural networks at circuit level and testing their functionality. Research into hardwarebased artificial neural networks is important because they are energy-efficient. Furthermore to calculating the variations, the statistical model can be used to determine what influence the cumulative distribution function of switching has on the variations and which behavior provides the best results for the hardwarebased artificial neural network. Some memristive devices exhibit multi-level behavior due to defects in the switching layer. The number of these defects and the optimal amount can be estimated.}, language = {en} } @misc{DerschPerezWengeretal., author = {Dersch, Nadine and Perez, Eduardo and Wenger, Christian and Schwarz, Mike and Iniguez, Benjamin and Kloes, Alexander}, title = {A closed-form model for programming of oxide-based resistive random access memory cells derived from the Stanford model}, series = {Solid-state electronics}, volume = {230}, journal = {Solid-state electronics}, publisher = {Elsevier BV}, address = {Amsterdam}, issn = {0038-1101}, doi = {10.1016/j.sse.2025.109238}, pages = {1 -- 5}, abstract = {This paper presents a closed-form model for pulse-based programming of oxide-based resistive random access memory devices. The Stanford model is used as a basis and solved in a closed-form for the programming cycle. A constant temperature is set for this solution. With the closed-form model, the state of the device after programming or the required programming settings for achieving a specific device conductance can be calculated directly and quickly. The Stanford model requires time-consuming iterative calculations for high accuracy in transient analysis, which is not necessary for the closed-form model. The closed-form model is scalable across different programming pulse widths and voltages.}, language = {en} } @misc{WenBaroniMistronietal., author = {Wen, Jianan and Baroni, Andrea and Mistroni, Alberto and Perez, Eduardo and Zambelli, Cristian and Wenger, Christian and Krstic, Milos and Bolzani P{\"o}hls, Leticia Maria}, title = {ReDiM : an efficient strategy for read disturb mitigation in RRAM-based accelerators}, series = {2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS)}, journal = {2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS)}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {979-8-3315-3334-2}, doi = {10.1109/IOLTS65288.2025.11117065}, pages = {1 -- 7}, abstract = {Resistive RAM (RRAM) has emerged as a promising non-volatile memory technology for implementing energy-efficient hardware accelerators within the in-memory computing (IMC) paradigm. However, due to the immature fabrication process and inherent material instabilities, frequent read operations during computations can induce read disturb effects, leading to unintended resistance drift and potential data corruption. Existing mitigation approaches primarily focus on detecting read disturb effects and triggering memory refresh operations. In this work, we propose an architecture-level solution that mitigates read disturb in RRAM-based accelerators. Our strategy employs crossbar duplication and decomposes the single high input pulse into two lower-amplitude pulses, effectively minimizing the risk of read disturb. To validate our approach, we develop a simulation framework that incorporates measurement data from characterized RRAM devices under read disturb stress conditions. Experimental results on VGG-8 with CIFAR-10 demonstrate that the proposed method significantly mitigates inference accuracy degradation caused by read disturb in RRAM-based accelerators, while incurring modest area and energy overheads of 12.32\% and 2.15\%, respectively. This work provides a practical and scalable solution for enhancing the robustness of RRAM-based accelerators in edge and high-performance computing applications.}, language = {en} } @misc{BlumensteinPerezWengeretal., author = {Blumenstein, Alan and P{\´e}rez, Eduardo and Wenger, Christian and Dersch, Nadine and Kloes, Alexander and I{\~n}{\´i}guez, Benjam{\´i}n and Schwarz, Mike}, title = {Exploring variability and quantization effects in artificial neural networks using the MNIST dataset}, series = {Solid-state electronics}, volume = {232}, journal = {Solid-state electronics}, publisher = {Elsevier BV}, address = {Amsterdam}, issn = {0038-1101}, doi = {10.1016/j.sse.2025.109296}, pages = {1 -- 4}, abstract = {This paper investigates the impact of introducing variability to trained neural networks and examines the effects of variability and quantization on network accuracy. The study utilizes the MNIST dataset to evaluate various Multi-Layer Perceptron configurations: a baseline model with a Single-Layer Perceptron and an extended model with multiple hidden nodes. The effects of Cycle-to-Cycle variability on network accuracy are explored by varying parameters such as the standard deviation to simulate dynamic changes in network weights. In particular, the performance differences between the Single-Layer Perceptron and the Multi-Layer Perceptron with hidden layers are analyzed, highlighting the network's robustness to stochastic perturbations. These results provide insights into the effects of quantization and network architecture on accuracy under varying levels of variability.}, language = {en} } @misc{PerezMaldonadoPechmannetal., author = {Perez, Eduardo and Maldonado, David and Pechmann, Stefan and Reddy, Keerthi Dorai Swamy and Uhlmann, Max and Hagelauer, Amelie and Roldan, Juan Bautista and Wenger, Christian}, title = {Impact of the series resistance on switching characteristics of 1T1R HfO₂-based RRAM devices}, series = {2025 15th Spanish Conference on Electron Devices (CDE)}, journal = {2025 15th Spanish Conference on Electron Devices (CDE)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {Piscataway, NJ}, isbn = {979-8-3315-9618-7}, doi = {10.1109/CDE66381.2025.11038868}, pages = {1 -- 4}, abstract = {This study investigates the influence of the series resistance (RS) on the switching characteristics of 1-transistor-1-resistor (1T1R) RRAM devices based on HfO2 and Al:HfO₂ dielectrics. Intrinsic RS values were extracted from I-V characteristics measured over 50 Reset-Set cycles at various gate voltages (VG) by using a numerical transformation method. Results reveal the contribution of the transistor's resistance to the overall RS. A linear relationship between RS values and Set transition voltages (VTS) was found, with larger RS values amplifying the variability in switching parameters. Comparative analysis of cumulative distribution functions (CDFs) highlights differences between technologies, showing lower VTS values as well as lower sensitivity to RS for Al:HfO₂-based devices. These findings underscore the critical role of RS in modeling and optimizing the performance of RRAM devices for reliable operation.}, language = {en} } @misc{MaldonadoAcalOrtizetal., author = {Maldonado, D. and Acal, C. and Ortiz, H. and Navas-Gomez, F. and Cantudo, A. and Wenger, Christian and P{\´e}rez, Eduardo and Rold{\´a}n, J.B.}, title = {Variability in HfO₂-based memristors under pulse operation}, series = {Microelectronic engineering}, volume = {304}, journal = {Microelectronic engineering}, publisher = {Elsevier BV}, address = {Amsterdam}, issn = {0167-9317}, doi = {10.1016/j.mee.2026.112445}, pages = {1 -- 8}, abstract = {We have studied device-to-device variability in TiN/Ti/HfO2/TiN devices under pulse operation. We measured extensively memristive devices that are CMOS integrated with different pulse trains, changing the pulse width and amplitude for groups of more than one hundred devices. The statistical parameters of the measured current were extracted to better understand the device physics under the pulse operation regime. An analytical model to describe synaptic depression and potentiation behavior in the device conductance is introduced, it fits accurately the means of the current data for all the pulse trains under study. In addition, an explanation of the measurements is enlightened with kinetic Monte Carlo simulations that allow the study of resistive switching at the atomic level. Finally, the probability distribution functions of the measured currents in some of the pulses within the pulse series employed are analyzed to extract the probability distribution that works better. A proposal for the implementation of device-to-device variability in the Stanford models is introduced.}, language = {en} }