@misc{PerezPerezAvilaRomeroZalizetal., author = {P{\´e}rez, Eduardo and P{\´e}rez-{\´A}vila, Antonio Javier and Romero-Zaliz, Roc{\´i}o and Mahadevaiah, Mamathamba Kalishettyhalli and P{\´e}rez-Bosch Quesada, Emilio and Roldan, Juan Bautista and Jim{\´e}nez-Molinos, Francisco and Wenger, Christian}, title = {Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing}, series = {Electronics (MDPI)}, volume = {10}, journal = {Electronics (MDPI)}, number = {9}, issn = {2079-9292}, doi = {10.3390/electronics10091084}, pages = {15}, abstract = {Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8×8 vector-matrixmultiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6\% compared with the use of non-optimized parameters.}, language = {en} } @misc{PerezBoschQuesadaRomeroZalizPerezetal., author = {P{\´e}rez-Bosch Quesada, Emilio and Romero-Zaliz, Roc{\´i}o and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Reuben, John and Schubert, Markus Andreas and Jim{\´e}nez-Molinos, Francisco and Rold{\´a}n, Juan Bautista and Wenger, Christian}, title = {Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems}, series = {Electronics (MDPI)}, volume = {10}, journal = {Electronics (MDPI)}, number = {6}, issn = {2079-9292}, doi = {10.3390/electronics10060645}, pages = {13}, abstract = {In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.}, language = {en} } @misc{PechmannMaiVoelkeletal., author = {Pechmann, Stefan and Mai, Timo and V{\"o}lkel, Matthias and Mahadevaiah, Mamathamba Kalishettyhalli and P{\´e}rez, Eduardo and Perez-Bosch Quesada, Emilio and Reichenbach, Marc and Wenger, Christian and Hagelauer, Amelie}, title = {A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells}, series = {Electronics}, volume = {10}, journal = {Electronics}, number = {5}, issn = {2079-9292}, doi = {10.3390/electronics10050530}, pages = {17}, abstract = {In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.}, language = {en} } @misc{PerezMahadevaiahPerezBoschQuesadaetal., author = {P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Perez-Bosch Quesada, Emilio and Wenger, Christian}, title = {Variability and Energy Consumption Tradeoffs in Multilevel Programming of RRAM Arrays}, series = {IEEE Transactions on Electron Devices}, volume = {68}, journal = {IEEE Transactions on Electron Devices}, number = {6}, issn = {0018-9383}, doi = {10.1109/TED.2021.3072868}, pages = {2693 -- 2698}, abstract = {Achieving a reliable multi-level programming operation in resistive random access memory (RRAM) arrays is still a challenging task. In this work, we assessed the impact of the voltage step value used by the programming algorithm on the device-to-device (DTD) variability of the current distributions of four conductive levels and on the energy consumption featured by programming 4-kbit HfO2-based RRAM arrays. Two different write-verify algorithms were considered and compared, namely, the incremental gate voltage with verify algorithm (IGVVA) and the incremental step pulse with verify algorithm (ISPVA). By using the IGVVA, a main trade-off has to be taken into account since reducing the voltage step leads to a smaller DTD variability at the cost of a strong increase in the energy consumption. Although the ISPVA can not reduce the DTD variability as much as the IGVVA, its voltage step can be decreased in order to reduce the energy consumption with almost no impact on the DTD variability. Therefore, the final decision on which algorithm to employ should be based on the specific application targeted for the RRAM array.}, language = {en} } @misc{PerezBoschQuesadaPerezMahadevaiahetal., author = {Perez-Bosch Quesada, Emilio and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Wenger, Christian}, title = {Memristive-based in-memory computing: from device to large-scale CMOS integration}, series = {Neuromorphic Computing and Engineering}, volume = {1}, journal = {Neuromorphic Computing and Engineering}, number = {2}, issn = {2634-4386}, doi = {10.1088/2634-4386/ac2cd4}, pages = {8}, abstract = {With the rapid emergence of in-memory computing systems based on memristive technology, the integration of such memory devices in large-scale architectures is one of the main aspects to tackle. In this work we present a study of HfO2-based memristive devices for their integration in large-scale CMOS systems, namely 200 mm wafers. The DC characteristics of single metal-insulator-metal devices are analyzed taking under consideration device-to-device variabilities and switching properties. Furthermore, the distribution of the leakage current levels in the pristine state of the samples are analyzed and correlated to the amount of formingless memristors found among the measured devices. Finally, the obtained results are fitted into a physic-based compact model that enables their integration into larger-scale simulation environments.}, language = {en} } @misc{PerezMaldonadoAcaletal., author = {P{\´e}rez, Eduardo and Maldonado, David and Acal, Christian and Ruiz-Castro, Juan Eloy and Aguilera, Ana Mar{\´i}a and Jimenez-Molinos, Francisco and Roldan, Juan Bautista and Wenger, Christian}, title = {Advanced Temperature Dependent Statistical Analysis of Forming Voltage Distributions for Three Different HfO2-Based RRAM Technologies}, series = {Solid State Electronics}, volume = {176}, journal = {Solid State Electronics}, issn = {0038-1101}, pages = {6}, abstract = {In this work, voltage distributions of forming operations are analyzed by using an advanced statistical approach based on phase-type distributions (PHD). The experimental data were collected from batches of 128 HfO2-based RRAM devices integrated in 4-kbit arrays. Three di erent switching oxides, namely, polycrystalline HfO2, amorphous HfO2, and Al-doped HfO2, were tested in the temperature range from -40 to 150 oC. The variability of forming voltages has been usually studied by using the Weibull distribution (WD). However, the performance of the PHD analysis demonstrated its ability to better model this crucial operation. The capacity of the PHD to reproduce the experimental data has been validated by means of the Kolmogorov-Smirnov test, while the WD failed in many of the cases studied. In addition, PHD allows to extract information about intermediate probabilistic states that occur in the forming process and the transition probabilities between them; in this manner, we can deepen on the conductive lament formation physics. In particular, the number of intermediate states can be related to the device variability.}, language = {en} } @misc{RomeroZalizPerezJimenezMolinosetal., author = {Romero-Zaliz, Roc{\´i}o and P{\´e}rez, Eduardo and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {Study of Quantized Hardware Deep Neural Networks Based on Resistive Switching Devices, Conventional versus Convolutional Approaches}, series = {Electronics (MDPI)}, volume = {10}, journal = {Electronics (MDPI)}, number = {3}, issn = {2079-9292}, doi = {10.3390/electronics10030346}, pages = {14}, abstract = {A comprehensive analysis of two types of artificial neural networks (ANN) is performed to assess the influence of quantization on the synaptic weights. Conventional multilayer-perceptron (MLP) and convolutional neural networks (CNN) have been considered by changing their features in the training and inference contexts, such as number of levels in the quantization process, the number of hidden layers on the network topology, the number of neurons per hidden layer, the image databases, the number of convolutional layers, etc. A reference technology based on 1T1R structures with bipolar memristors including HfO2 dielectrics was employed, accounting for different multilevel schemes and the corresponding conductance quantization algorithms. The accuracy of the image recognition processes was studied in depth. This type of studies are essential prior to hardware implementation of neural networks. The obtained results support the use of CNNs for image domains. This is linked to the role played by convolutional layers at extracting image features and reducing the data complexity. In this case, the number of synaptic weights can be reduced in comparison to conventional MLPs.}, language = {en} } @misc{MiloAnzaloneZambellietal., author = {Milo, Valerio and Anzalone, Francesco and Zambelli, Cristian and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Ossorio, {\´O}scar G. and Olivo, Piero and Wenger, Christian and Ielmini, Daniele}, title = {Optimized programming algorithms for multilevel RRAM in hardware neural networks}, series = {IEEE International Reliability Physics Symposium (IRPS), 2021}, journal = {IEEE International Reliability Physics Symposium (IRPS), 2021}, isbn = {978-1-7281-6894-4}, issn = {1938-1891}, doi = {10.1109/IRPS46558.2021.9405119}, abstract = {A key requirement for RRAM in neural network accelerators with a large number of synaptic parameters is the multilevel programming. This is hindered by resistance imprecision due to cycle-to-cycle and device-to-device variations. Here, we compare two multilevel programming algorithms to minimize resistance variations in a 4-kbit array of HfO 2 RRAM. We show that gate-based algorithms have the highest reliability. The optimized scheme is used to implement a neural network with 9-level weights, achieving 91.5\% (vs. software 93.27\%) in MNIST recognition.}, language = {en} } @misc{PetrykDykaPerezetal., author = {Petryk, Dmytro and Dyka, Zoya and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Kabin, Ievgen and Wenger, Christian and Langend{\"o}rfer, Peter}, title = {Evaluation of the Sensitivity of RRAM Cells to Optical Fault Injection Attacks}, series = {EUROMICRO Conference on Digital System Design (DSD 2020), Special Session: Architecture and Hardware for Security Applications (AHSA)}, journal = {EUROMICRO Conference on Digital System Design (DSD 2020), Special Session: Architecture and Hardware for Security Applications (AHSA)}, isbn = {978-1-7281-9535-3}, issn = {978-1-7281-9536-0}, doi = {10.1109/DSD51259.2020.00047}, pages = {8}, language = {en} } @misc{RomeroZalizPerezJimenezMolinosetal., author = {Romero-Zaliz, Roc{\´i}o and P{\´e}rez, Eduardo and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {Influence of variability on the performance of HfO2 memristor-based convolutional neural networks}, series = {Solid State Electronics}, volume = {185}, journal = {Solid State Electronics}, issn = {0038-1101}, doi = {10.1016/j.sse.2021.108064}, pages = {5}, abstract = {A study of convolutional neural networks (CNNs) was performed to analyze the influence of quantization and variability in the network synaptic weights. Different CNNs were considered accounting for the number of convolutional layers, size of the filters in the convolutional layer, number of neurons in the final network layers and different sets of quantization levels. The conductance levels of fabricated 1T1R structures based on HfO2 memristors were considered as reference for four or eight level quantization processes at the inference stage of the CNNs, which were previous trained with the MNIST dataset. We also included the variability of the experimental conductance levels that was found to be Gaussian distributed and was correspondingly modeled for the synaptic weight implementation.}, language = {en} } @misc{OssorioVinuesaGarciaetal., author = {Ossorio, {\´O}scar G. and Vinuesa, Guillermo and Garcia, Hector and Sahelices, Benjamin and Due{\~n}as, Salvador and Cast{\´a}n, Helena and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Wenger, Christian}, title = {Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications}, series = {ECS Transactions}, volume = {102}, journal = {ECS Transactions}, number = {2}, issn = {1938-6737}, doi = {10.1149/10202.0029ecst}, pages = {29 -- 35}, abstract = {The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.}, language = {en} } @misc{BaroniZambelliOlivoetal., author = {Baroni, Andrea and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele}, title = {Tackling the Low Conductance State Drift through Incremental Reset and Verify in RRAM Arrays}, series = {2021 IEEE International Integrated Reliability Workshop (IIRW), South Lake Tahoe, CA, USA, 10 December 2021}, journal = {2021 IEEE International Integrated Reliability Workshop (IIRW), South Lake Tahoe, CA, USA, 10 December 2021}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {978-1-6654-1794-5}, issn = {2374-8036}, doi = {10.1109/IIRW53245.2021.9635613}, pages = {5}, abstract = {Resistive switching memory (RRAM) is a promising technology for highly efficient computing scenarios. RRAM arrays enabled the acceleration of neural networks for artificial intelligence and the creation of In-Memory Computing circuits. However, the arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation in those applications. Among those, one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are fundamental for an accurate Multi-level conductance operation. In this work, we tackle the issue by developing an Incremental Reset and Verify technique showing enhanced variability and reliability features compared with a traditional refresh-based approach.}, language = {en} } @misc{RomeroZalizCantudoPerezetal., author = {Romero-Zaliz, Rocio and Cantudo, Antonio and P{\´e}rez, Eduardo and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {An Analysis on the Architecture and the Size of Quantized Hardware Neural Networks Based on Memristors}, series = {Electronics (MDPI)}, volume = {10}, journal = {Electronics (MDPI)}, number = {24}, issn = {2079-9292}, doi = {10.3390/electronics10243141}, abstract = {We have performed different simulation experiments in relation to hardware neural networks (NN) to analyze the role of the number of synapses for different NN architectures in the network accuracy, considering different datasets. A technology that stands upon 4-kbit 1T1R ReRAM arrays, where resistive switching devices based on HfO2 dielectrics are employed, is taken as a reference. In our study, fully dense (FdNN) and convolutional neural networks (CNN) were considered, where the NN size in terms of the number of synapses and of hidden layer neurons were varied. CNNs work better when the number of synapses to be used is limited. If quantized synaptic weights are included, we observed thatNNaccuracy decreases significantly as the number of synapses is reduced; in this respect, a trade-off between the number of synapses and the NN accuracy has to be achieved. Consequently, the CNN architecture must be carefully designed; in particular, it was noticed that different datasets need specific architectures according to their complexity to achieve good results. It was shown that due to the number of variables that can be changed in the optimization of a NN hardware implementation, a specific solution has to be worked in each case in terms of synaptic weight levels, NN architecture, etc.}, language = {en} } @misc{PetrykDykaPerezetal., author = {Petryk, Dmytro and Dyka, Zoya and P{\´e}rez, Eduardo and Kabin, Ievgen and Katzer, Jens and Sch{\"a}ffner, Jan and Langend{\"o}rfer, Peter}, title = {Sensitivity of HfO2-based RRAM Cells to Laser Irradiation}, series = {Microprocessors and Microsystems}, journal = {Microprocessors and Microsystems}, number = {87}, issn = {0141-9331}, doi = {10.1016/j.micpro.2021.104376}, language = {en} }