@misc{PerezAvilaGonzalezCorderoPerezetal., author = {Perez-Avila, Antonio Javier and Gonzalez-Cordero, Gerardo and P{\´e}rez, Eduardo and Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Wenger, Christian and Roldan, Juan Bautista and Jimenez-Molinos, Francisco}, title = {Behavioral modeling of multilevel HfO2-based memristors for neuromorphic circuit simulation}, series = {XXXV Conference on Design of Circuits and Integrated Systems (DCIS), Segovia, Spain}, journal = {XXXV Conference on Design of Circuits and Integrated Systems (DCIS), Segovia, Spain}, doi = {10.1109/DCIS51330.2020.9268652}, abstract = {An artificial neural network based on resistive switching memristors is implemented and simulated in LTspice. The influence of memristor variability and the reduction of the continuous range of synaptic weights into a discrete set of conductance levels is analyzed. To do so, a behavioral model is proposed for multilevel resistive switching memristors based on Al-doped HfO2 dielectrics, and it is implemented in a spice based circuit simulator. The model provides an accurate description of the conductance in the different conductive states in addition to describe the device-to-device variability}, language = {en} } @misc{PerezPerezAvilaRomeroZalizetal., author = {P{\´e}rez, Eduardo and P{\´e}rez-{\´A}vila, Antonio Javier and Romero-Zaliz, Roc{\´i}o and Mahadevaiah, Mamathamba Kalishettyhalli and P{\´e}rez-Bosch Quesada, Emilio and Roldan, Juan Bautista and Jim{\´e}nez-Molinos, Francisco and Wenger, Christian}, title = {Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing}, series = {Electronics (MDPI)}, volume = {10}, journal = {Electronics (MDPI)}, number = {9}, issn = {2079-9292}, doi = {10.3390/electronics10091084}, pages = {15}, abstract = {Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8×8 vector-matrixmultiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6\% compared with the use of non-optimized parameters.}, language = {en} } @misc{PerezBoschQuesadaRomeroZalizPerezetal., author = {P{\´e}rez-Bosch Quesada, Emilio and Romero-Zaliz, Roc{\´i}o and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Reuben, John and Schubert, Markus Andreas and Jim{\´e}nez-Molinos, Francisco and Rold{\´a}n, Juan Bautista and Wenger, Christian}, title = {Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems}, series = {Electronics (MDPI)}, volume = {10}, journal = {Electronics (MDPI)}, number = {6}, issn = {2079-9292}, doi = {10.3390/electronics10060645}, pages = {13}, abstract = {In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.}, language = {en} } @misc{PechmannMaiVoelkeletal., author = {Pechmann, Stefan and Mai, Timo and V{\"o}lkel, Matthias and Mahadevaiah, Mamathamba Kalishettyhalli and P{\´e}rez, Eduardo and Perez-Bosch Quesada, Emilio and Reichenbach, Marc and Wenger, Christian and Hagelauer, Amelie}, title = {A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells}, series = {Electronics}, volume = {10}, journal = {Electronics}, number = {5}, issn = {2079-9292}, doi = {10.3390/electronics10050530}, pages = {17}, abstract = {In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.}, language = {en} } @misc{PerezMahadevaiahPerezBoschQuesadaetal., author = {P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Perez-Bosch Quesada, Emilio and Wenger, Christian}, title = {Variability and Energy Consumption Tradeoffs in Multilevel Programming of RRAM Arrays}, series = {IEEE Transactions on Electron Devices}, volume = {68}, journal = {IEEE Transactions on Electron Devices}, number = {6}, issn = {0018-9383}, doi = {10.1109/TED.2021.3072868}, pages = {2693 -- 2698}, abstract = {Achieving a reliable multi-level programming operation in resistive random access memory (RRAM) arrays is still a challenging task. In this work, we assessed the impact of the voltage step value used by the programming algorithm on the device-to-device (DTD) variability of the current distributions of four conductive levels and on the energy consumption featured by programming 4-kbit HfO2-based RRAM arrays. Two different write-verify algorithms were considered and compared, namely, the incremental gate voltage with verify algorithm (IGVVA) and the incremental step pulse with verify algorithm (ISPVA). By using the IGVVA, a main trade-off has to be taken into account since reducing the voltage step leads to a smaller DTD variability at the cost of a strong increase in the energy consumption. Although the ISPVA can not reduce the DTD variability as much as the IGVVA, its voltage step can be decreased in order to reduce the energy consumption with almost no impact on the DTD variability. Therefore, the final decision on which algorithm to employ should be based on the specific application targeted for the RRAM array.}, language = {en} } @misc{PerezBoschQuesadaPerezMahadevaiahetal., author = {Perez-Bosch Quesada, Emilio and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Wenger, Christian}, title = {Memristive-based in-memory computing: from device to large-scale CMOS integration}, series = {Neuromorphic Computing and Engineering}, volume = {1}, journal = {Neuromorphic Computing and Engineering}, number = {2}, issn = {2634-4386}, doi = {10.1088/2634-4386/ac2cd4}, pages = {8}, abstract = {With the rapid emergence of in-memory computing systems based on memristive technology, the integration of such memory devices in large-scale architectures is one of the main aspects to tackle. In this work we present a study of HfO2-based memristive devices for their integration in large-scale CMOS systems, namely 200 mm wafers. The DC characteristics of single metal-insulator-metal devices are analyzed taking under consideration device-to-device variabilities and switching properties. Furthermore, the distribution of the leakage current levels in the pristine state of the samples are analyzed and correlated to the amount of formingless memristors found among the measured devices. Finally, the obtained results are fitted into a physic-based compact model that enables their integration into larger-scale simulation environments.}, language = {en} } @misc{BischoffLeisePerezBoschQuesadaetal., author = {Bischoff, Carl and Leise, Jakob and Perez-Bosch Quesada, Emilio and P{\´e}rez, Eduardo and Wenger, Christian and Kloes, Alexander}, title = {Implementation of device-to-device and cycle-to-cycle variability of memristive devices in circuit simulations}, series = {Solid-State Electronics}, volume = {194}, journal = {Solid-State Electronics}, issn = {0038-1101}, doi = {10.1016/j.sse.2022.108321}, pages = {4}, abstract = {We present a statistical procedure for the extraction of parameters of a compact model for memristive devices. Thereby, in a circuit simulation the typical fluctuations of the current-voltage (I-V) characteristics from device-to-device (D2D) and from cycle-to-cycle (C2C) can be emulated. The approach is based on the Stanford model whose parameters play a key role to integrating D2D and C2C dispersion. The influence of such variabilities over the model's parameters is investigated by using a fitting algorithm fed with experimental data. After this, the statistical distributions of the parameters are used in a Monte Carlo simulation to reproduce the I-V D2D and C2C dispersions which show a good agreement to the measured curves. The results allow the simulation of the on/off current variation for the design of RRAM cells or memristor-based artificial neural networks.}, language = {en} } @misc{MahadevaiahPerezLiskeretal., author = {Mahadevaiah, Mamathamba Kalishettyhalli and P{\´e}rez, Eduardo and Lisker, Marco and Schubert, Markus Andreas and Perez-Bosch Quesada, Emilio and Wenger, Christian and Mai, Andreas}, title = {Modulating the Filamentary-Based Resistive Switching Properties of HfO2 Memristive Devices by Adding Al2O3 Layers}, series = {Electronics : open access journal}, volume = {11}, journal = {Electronics : open access journal}, number = {10}, issn = {2079-9292}, doi = {10.3390/electronics11101540}, pages = {14}, abstract = {The resistive switching properties of HfO2 based 1T-1R memristive devices are electrically modified by adding ultra-thin layers of Al2O3 into the memristive device. Three different types of memristive stacks are fabricated in the 130 nm CMOS technology of IHP. The switching properties of the memristive devices are discussed with respect to forming voltages, low resistance state and high resistance state characteristics and their variabilities. The experimental I-V characteristics of set and reset operations are evaluated by using the quantum point contact model. The properties of the conduction filament in the on and off states of the memristive devices are discussed with respect to the model parameters obtained from the QPC fit.}, language = {en} } @misc{PerezMahadevaiahPerezBoschQuesadaetal., author = {P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Perez-Bosch Quesada, Emilio and Wenger, Christian}, title = {In-depth characterization of switching dynamics in amorphous HfO2 memristive arrays for the implementation of synaptic updating rules}, series = {Japanese Journal of Applied Physics}, volume = {61}, journal = {Japanese Journal of Applied Physics}, issn = {0021-4922}, doi = {10.35848/1347-4065/ac6a3b}, pages = {1 -- 7}, abstract = {Accomplishing truly analog conductance modulation in memristive arrays is crucial in order to implement the synaptic plasticity in hardware-based neuromorphic systems. In this paper, such a feature was addressed by exploiting the inherent stochasticity of switching dynamics in amorphous HfO2 technology. A thorough statistical analysis of experimental characteristics measured in 4 kbit arrays by using trains of identical depression/potentiation pulses with different voltage amplitudes and pulse widths provided the key to develop two different updating rules and to define their optimal programming parameters. The first rule is based on applying a specific number of identical pulses until the conductance value achieves the desired level. The second one utilized only one single pulse with a particular amplitude to achieve the targeted conductance level. In addition, all the results provided by the statistical analysis performed may play an important role in understanding better the switching behavior of this particular technology.}, language = {en} } @misc{BogunPerezBoschQuesadaPerezetal., author = {Bogun, Nicolas and Perez-Bosch Quesada, Emilio and P{\´e}rez, Eduardo and Wenger, Christian and Kloes, Alexander and Schwarz, Mike}, title = {Analytical Calculation of Inference in Memristor-based Stochastic Artificial Neural Networks}, series = {29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES), 23-24 June 2022 , Wrocław, Poland}, journal = {29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES), 23-24 June 2022 , Wrocław, Poland}, isbn = {978-83-63578-22-0}, doi = {10.23919/MIXDES55591.2022.9838321}, pages = {83 -- 88}, abstract = {The impact of artificial intelligence on human life has increased significantly in recent years. However, as the complexity of problems rose aswell, increasing system features for such amount of data computation became troublesome due to the von Neumann's computer architecture. Neuromorphic computing aims to solve this problem by mimicking the parallel computation of a human brain. For this approach, memristive devices are used to emulate the synapses of a human brain. Yet, common simulations of hardware based networks require time consuming Monte-Carlo simulations to take into account the stochastic switching of memristive devices. This work presents an alternative concept making use of the convolution of the probability distribution functions (PDF) of memristor currents by its equivalent multiplication in Fourier domain. An artificial neural network is accordingly implemented to perform the inference stage with handwritten digits.}, language = {en} } @misc{PerezMaldonadoPerezBoschQuesadaetal., author = {P{\´e}rez, Eduardo and Maldonado, David and Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Jimenez-Molinos, Francisco and Wenger, Christian}, title = {Parameter Extraction Methods for Assessing Device-to-Device and Cycle-to-Cycle Variability of Memristive Devices at Wafer Scale}, series = {IEEE Transactions on Electron Devices}, volume = {70}, journal = {IEEE Transactions on Electron Devices}, number = {1}, issn = {0018-9383}, doi = {10.1109/TED.2022.3224886}, pages = {360 -- 365}, abstract = {The stochastic nature of the resistive switching (RS) process in memristive devices makes device-to-device (DTD) and cycle-to-cycle (CTC) variabilities relevant magnitudes to be quantified and modeled. To accomplish this aim, robust and reliable parameter extraction methods must be employed. In this work, four different extraction methods were used at the production level (over all the 108 devices integrated on 200-mm wafers manufactured in the IHP 130-nm CMOS technology) in order to obtain the corresponding collection of forming, reset, and set switching voltages. The statistical analysis of the experimental data (mean and standard deviation (SD) values) was plotted by using heat maps, which provide a good summary of the whole data at a glance and, in addition, an easy manner to detect inhomogeneities in the fabrication process.}, language = {en} } @misc{PerezBoschQuesadaMistroniJiaetal., author = {Perez-Bosch Quesada, Emilio and Mistroni, Alberto and Jia, Ruolan and Dorai Swamy Reddy, Keerthi and Reichmann, Felix and Castan, Helena and Due{\~n}as, Salvador and Wenger, Christian and Perez, Eduardo}, title = {Forming and resistive switching of HfO₂-based RRAM devices at cryogenic temperature}, series = {IEEE Electron Device Letters}, volume = {45}, journal = {IEEE Electron Device Letters}, number = {12}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, issn = {0741-3106}, doi = {10.1109/LED.2024.3485873}, pages = {2391 -- 2394}, abstract = {Reliable data storage technologies able to operate at cryogenic temperatures are critical to implement scalable quantum computers and develop deep-space exploration systems, among other applications. Their scarce availability is pushing towards the development of emerging memories that can perform such storage in a non-volatile fashion. Resistive Random-Access Memories (RRAM) have demonstrated their switching capabilities down to 4K. However, their operability at lower temperatures still remain as a challenge. In this work, we demonstrate for the first time the forming and resistive switching capabilities of CMOS-compatible RRAM devices at 1.4K. The HfO2-based devices are deployed following an array of 1-transistor-1-resistor (1T1R) cells. Their switching performance at 1.4K was also tested in the multilevel-cell (MLC) approach, storing up to 4 resistance levels per cell.}, language = {en} } @misc{UhlmannRizziWenetal., author = {Uhlmann, Max and Rizzi, Tommaso and Wen, Jianan and P{\´e}rez-Bosch Quesada, Emilio and Al Beattie, Bakr and Ochs, Karlheinz and P{\´e}rez, Eduardo and Ostrovskyy, Philip and Carta, Corrado and Wenger, Christian and Kahmen, Gerhard}, title = {LUT-based RRAM model for neural accelerator circuit simulation}, series = {Proceedings of the 18th ACM International Symposium on Nanoscale Architectures}, journal = {Proceedings of the 18th ACM International Symposium on Nanoscale Architectures}, publisher = {ACM}, address = {New York, NY, USA}, doi = {10.1145/3611315.3633273}, pages = {1 -- 6}, abstract = {Neural hardware accelerators have been proven to be energy-efficient when used to solve tasks which can be mapped into an artificial neural network (ANN) structure. Resistive random-access memories (RRAMs) are currently under investigation together with several different memristive devices as promising technologies to build such accelerators combined together with complementary metal-oxide semiconductor (CMOS)-technologies in integrated circuits (ICs). While many research groups are actively developing sophisticated physical-based representations to better understand the underlying phenomena characterizing these devices, not much work has been dedicated to exploit the trade-off between simulation time and accuracy in the definition of low computational demanding models suitable to be used at many abstraction layers. Indeed, the design of complex mixed-signal systems as a neural hardware accelerators requires frequent interaction between the application- and the circuit-level that can be enabled only with the support of accurate and fast-simulating devices' models. In this work, we propose a solution to fill the aforementioned gap with a lookup table (LUT)-based Verilog-A model of IHP's 1-transistor-1-RRAM (1T1R) cell. In addition, the implementation challenges of conveying the communication between the abstract ANN simulation and the circuital analysis are tackled with a design flow for resistive neural hardware accelerators that features a custom Python wrapper. As a demonstration of the proposed design flow and 1T1R model, an ANN for the MNIST handwritten digit recognition task is assessed with the last layer verified in circuit simulation. The obtained recognition confidence intervals show a considerable discrepancy between the purely application-level PyTorch simulation and the proposed design flow which spans across the abstraction layers down to the circuital analysis.}, language = {en} } @misc{KloesBischoffLeiseetal., author = {Kloes, Alexander and Bischoff, Carl and Leise, Jakob and Perez-Bosch Quesada, Emilio and Wenger, Christian and P{\´e}rez, Eduardo}, title = {Stochastic switching of memristors and consideration in circuit simulation}, series = {Solid State Electronics}, volume = {201}, journal = {Solid State Electronics}, issn = {0038-1101}, doi = {10.1016/j.sse.2023.108606}, abstract = {We explore the stochastic switching of oxide-based memristive devices by using the Stanford model for circuit simulation. From measurements, the device-to-device (D2D) and cycle-to-cycle (C2C) statistical variation is extracted. In the low-resistive state (LRS) dispersion by D2D variability is dominant. In the high-resistive state (HRS) C2C dispersion becomes the main source of fluctuation. A statistical procedure for the extraction of parameters of the compact model is presented. Thereby, in a circuit simulation the typical D2D and C2C fluctuations of the current-voltage (I-V) characteristics can be emulated by extracting statistical parameters of key model parameters. The statistical distributions of the parameters are used in a Monte Carlo simulation to reproduce the I-V D2D and C2C dispersions which show a good agreement to the measured curves. The results allow the simulation of the on/off current variation for the design of memory cells or can be used to emulate the synaptic behavior of these devices in artificial neural networks realized by a crossbar array of memristors.}, language = {en} } @misc{PerezBoschQuesadaMahadevaiahRizzietal., author = {Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Rizzi, Tommaso and Wen, Jianan and Ulbricht, Markus and Krstic, Milos and Wenger, Christian and P{\´e}rez, Eduardo}, title = {Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing}, series = {IEEE Transactions on Electron Devices}, volume = {70}, journal = {IEEE Transactions on Electron Devices}, number = {4}, issn = {0018-9383}, doi = {10.1109/TED.2023.3244509}, pages = {2009 -- 2014}, abstract = {Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of 8x8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices' nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems.}, language = {en} } @misc{DerschPerezBoschQuesadaPerezetal., author = {Dersch, Nadine and Perez-Bosch Quesada, Emilio and P{\´e}rez, Eduardo and Wenger, Christian and Roemer, Christian and Schwarz, Mike and Kloes, Alexander}, title = {Efficient circuit simulation of a memristive crossbar array with synaptic weight variability}, series = {Solid State Electronics}, volume = {209}, journal = {Solid State Electronics}, issn = {0038-1101}, doi = {10.1016/j.sse.2023.108760}, abstract = {In this paper, we present a method for highly-efficient circuit simulation of a hardware-based artificial neural network realized in a memristive crossbar array. The statistical variability of the devices is considered by a noise-based simulation technique. For the simulation of a crossbar array with 8 synaptic weights in Cadence Virtuoso the new approach shows a more than 200x speed improvement compared to a Monte Carlo approach, yielding the same results. In addition, first results of an ANN with more than 15,000 memristive devices classifying test data of the MNIST dataset are shown, for which the speed improvement is expected to be several orders of magnitude. Furthermore, the influence on the classification of parasitic resistances of the connection lines in the crossbar is shown.}, language = {en} } @misc{UhlmannPerezBoschQuesadaFritscheretal., author = {Uhlmann, Max and P{\´e}rez-Bosch Quesada, Emilio and Fritscher, Markus and P{\´e}rez, Eduardo and Schubert, Markus Andreas and Reichenbach, Marc and Ostrovskyy, Philip and Wenger, Christian and Kahmen, Gerhard}, title = {One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing}, series = {21st IEEE Interregional NEWCAS Conference (NEWCAS)}, journal = {21st IEEE Interregional NEWCAS Conference (NEWCAS)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-0024-6}, issn = {2474-9672}, doi = {10.1109/NEWCAS57931.2023.10198073}, pages = {5}, abstract = {The use of resistive random-access memory (RRAM) for in-memory computing (IMC) architectures has significantly improved the energy-efficiency of artificial neural networks (ANN) over the past years. Current RRAM-technologies are physically limited to a defined unambiguously distinguishable number of stable states and a maximum resistive value and are compatible with present complementary metal-oxide semiconductor (CMOS)-technologies. In this work, we improved the accuracy of current ANN models by using increased weight resolutions of memristive devices, combining two or more in-series RRAM cells, integrated in the back end of line (BEOL) of the CMOS process. Based on system level simulations, 1T2R devices were fabricated in IHP's 130nm SiGe:BiCMOS technology node, demonstrating an increased number of states. We achieved an increase in weight resolution from 3 bit in ITIR cells to 6.5 bit in our 1T2R cell. The experimental data of 1T2R devices gives indications for the performance and energy-efficiency improvement in ITNR arrays for ANN applications.}, language = {en} } @misc{MaldonadoCantudoPerezetal., author = {Maldonado, David and Cantudo, Antonio and P{\´e}rez, Eduardo and Romero-Zaliz, Rocio and Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {TiN/Ti/HfO2/TiN Memristive Devices for Neuromorphic Computing: From Synaptic Plasticity to Stochastic Resonance}, series = {Frontiers in Neuroscience}, volume = {17}, journal = {Frontiers in Neuroscience}, issn = {1662-4548}, doi = {10.3389/fnins.2023.1271956}, abstract = {We characterize TiN/Ti/HfO2/TiN memristive devices for neuromorphic computing. We analyze different features that allow the devices to mimic biological synapses and present the models to reproduce analytically some of the data measured. In particular, we have measured the spike timing dependent plasticity behavior in our devices and later on we have modeled it. The spike timing dependent plasticity model was implemented as the learning rule of a spiking neural network that was trained to recognize the MNIST dataset. Variability is implemented and its influence on the network recognition accuracy is considered accounting for the number of neurons in the network and the number of training epochs. Finally, stochastic resonance is studied as another synaptic feature.It is shown that this effect is important and greatly depends on the noise statistical characteristics.}, language = {en} } @misc{PerezBoschQuesadaRizziGuptaetal., author = {Perez-Bosch Quesada, Emilio and Rizzi, Tommaso and Gupta, Aditya and Mahadevaiah, Mamathamba Kalishettyhalli and Schubert, Andreas and Pechmann, Stefan and Jia, Ruolan and Uhlmann, Max and Hagelauer, Amelie and Wenger, Christian and P{\´e}rez, Eduardo}, title = {Multi-Level Programming on Radiation-Hard 1T1R Memristive Devices for In-Memory Computing}, series = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, journal = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-0240-0}, doi = {10.1109/CDE58627.2023.10339525}, pages = {4}, abstract = {This work presents a quasi-static electrical characterization of 1-transistor-1-resistor memristive structures designed following hardness-by-design techniques integrated in the CMOS fabrication process to assure multi-level capabilities in harsh radiation environments. Modulating the gate voltage of the enclosed layout transistor connected in series with the memristive device, it was possible to achieve excellent switching capabilities from a single high resistance state to a total of eight different low resistance states (more than 3 bits). Thus, the fabricated devices are suitable for their integration in larger in-memory computing systems and in multi-level memory applications. Index Terms—radiation-hard, hardness-by-design, memristive devices, Enclosed Layout Transistor, in-memory computing}, language = {en} } @misc{PerezMaldonadoMahadevaiahetal., author = {P{\´e}rez, Eduardo and Maldonado, David and Mahadevaiah, Mamathamba Kalishettyhalli and Perez-Bosch Quesada, Emilio and Cantudo, Antonio and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {A comparison of resistive switching parameters for memristive devices with HfO2 monolayers and Al2O3/HfO2 bilayers at the wafer scale}, series = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, journal = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-0240-0}, doi = {10.1109/CDE58627.2023.10339417}, pages = {5}, abstract = {Memristive devices integrated in 200 mm wafers manufactured in 130 nm CMOS technology with two different dielectrics, namely, a HfO2 monolayer and an Al2O3/HfO2 bilayer, have been measured. The cycle-to-cycle (C2C) and device-todevice (D2D) variability have been analyzed at the wafer scale using different numerical methods to extract the set (Vset) and reset (Vreset) voltages. Some interesting differences between both technologies were found in terms of switching characteristics}, language = {en} } @misc{UhlmannRizziWenetal., author = {Uhlmann, Max and Rizzi, Tommaso and Wen, Jianan and Quesada, Emilio P{\´e}rez-Bosch and Beattie, Bakr Al and Ochs, Karlheinz and P{\´e}rez, Eduardo and Ostrovskyy, Philip and Carta, Corrado and Wenger, Christian and Kahmen, Gerhard}, title = {End-to-end design flow for resistive neural accelerators}, series = {IEEE transactions on computer-aided design of integrated circuits and systems}, journal = {IEEE transactions on computer-aided design of integrated circuits and systems}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {0278-0070}, doi = {10.1109/TCAD.2025.3597237}, pages = {1 -- 5}, abstract = {Neural hardware accelerators have demonstrated notable energy efficiency in tackling tasks, which can be adapted to artificial neural network (ANN) structures. Research is currently directed towards leveraging resistive random-access memories (RRAMs) among various memristive devices. In conjunction with complementary metal-oxide semiconductor (CMOS) technologies within integrated circuits (ICs), RRAM devices are used to build such neural accelerators. In this study, we present a neural accelerator hardware design and verification flow, which uses a lookup table (LUT)-based Verilog-A model of IHP's one-transistor-one-RRAM (1T1R) cell. In particular, we address the challenges of interfacing between abstract ANN simulations and circuit analysis by including a tailored Python wrapper into the design process for resistive neural hardware accelerators. To demonstrate our concept, the efficacy of the proposed design flow, we evaluate an ANN for the MNIST handwritten digit recognition task, as well as for the CIFAR-10 image recognition task, with the last layer verified through circuit simulation. Additionally, we implement different versions of a 1T1R model, based on quasi-static measurement data, providing insights on the effect of conductance level spacing and device-to-device variability. The circuit simulations tackle both schematic and physical layout assessment. The resulting recognition accuracies exhibit significant differences between the purely application-level PyTorch simulation and our proposed design flow, highlighting the relevance of circuit-level validation for the design of neural hardware accelerators.}, language = {en} } @misc{PerezMaldonadoAcaletal., author = {P{\´e}rez, Eduardo and Maldonado, David and Acal, Christian and Ruiz-Castro, Juan Eloy and Aguilera, Ana Mar{\´i}a and Jimenez-Molinos, Francisco and Roldan, Juan Bautista and Wenger, Christian}, title = {Advanced Temperature Dependent Statistical Analysis of Forming Voltage Distributions for Three Different HfO2-Based RRAM Technologies}, series = {Solid State Electronics}, volume = {176}, journal = {Solid State Electronics}, issn = {0038-1101}, pages = {6}, abstract = {In this work, voltage distributions of forming operations are analyzed by using an advanced statistical approach based on phase-type distributions (PHD). The experimental data were collected from batches of 128 HfO2-based RRAM devices integrated in 4-kbit arrays. Three di erent switching oxides, namely, polycrystalline HfO2, amorphous HfO2, and Al-doped HfO2, were tested in the temperature range from -40 to 150 oC. The variability of forming voltages has been usually studied by using the Weibull distribution (WD). However, the performance of the PHD analysis demonstrated its ability to better model this crucial operation. The capacity of the PHD to reproduce the experimental data has been validated by means of the Kolmogorov-Smirnov test, while the WD failed in many of the cases studied. In addition, PHD allows to extract information about intermediate probabilistic states that occur in the forming process and the transition probabilities between them; in this manner, we can deepen on the conductive lament formation physics. In particular, the number of intermediate states can be related to the device variability.}, language = {en} } @misc{RomeroZalizPerezJimenezMolinosetal., author = {Romero-Zaliz, Roc{\´i}o and P{\´e}rez, Eduardo and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {Study of Quantized Hardware Deep Neural Networks Based on Resistive Switching Devices, Conventional versus Convolutional Approaches}, series = {Electronics (MDPI)}, volume = {10}, journal = {Electronics (MDPI)}, number = {3}, issn = {2079-9292}, doi = {10.3390/electronics10030346}, pages = {14}, abstract = {A comprehensive analysis of two types of artificial neural networks (ANN) is performed to assess the influence of quantization on the synaptic weights. Conventional multilayer-perceptron (MLP) and convolutional neural networks (CNN) have been considered by changing their features in the training and inference contexts, such as number of levels in the quantization process, the number of hidden layers on the network topology, the number of neurons per hidden layer, the image databases, the number of convolutional layers, etc. A reference technology based on 1T1R structures with bipolar memristors including HfO2 dielectrics was employed, accounting for different multilevel schemes and the corresponding conductance quantization algorithms. The accuracy of the image recognition processes was studied in depth. This type of studies are essential prior to hardware implementation of neural networks. The obtained results support the use of CNNs for image domains. This is linked to the role played by convolutional layers at extracting image features and reducing the data complexity. In this case, the number of synaptic weights can be reduced in comparison to conventional MLPs.}, language = {en} } @misc{SoltaniZarrinZahariMahadevaiahetal., author = {Soltani Zarrin, Pouya and Zahari, Finn and Mahadevaiah, Mamathamba Kalishettyhalli and P{\´e}rez, Eduardo and Kohlstedt, Hermann and Wenger, Christian}, title = {Neuromorphic on‑chip recognition of saliva samples of COPD and healthy controls using memristive devices}, series = {Scientific Reports}, volume = {10}, journal = {Scientific Reports}, issn = {2045-2322}, doi = {10.1038/s41598-020-76823-7}, abstract = {Chronic Obstructive Pulmonary Disease (COPD) is a life-threatening lung disease, affecting millions of people worldwide. Implementation of Machine Learning (ML) techniques is crucial for the effective management of COPD in home-care environments. However, shortcomings of cloud-based ML tools in terms of data safety and energy efficiency limit their integration with low-power medical devices. To address this, energy efficient neuromorphic platforms can be used for the hardware-based implementation of ML methods. Therefore, a memristive neuromorphic platform is presented in this paper for the on-chip recognition of saliva samples of COPD patients and healthy controls. The results of its performance evaluations showed that the digital neuromorphic chip is capable of recognizing unseen COPD samples with accuracy and sensitivity values of 89\% and 86\%, respectively. Integration of this technology into personalized healthcare devices will enable the better management of chronic diseases such as COPD.}, language = {en} } @misc{ZanottiPuglisiMiloetal., author = {Zanotti, Tommaso and Puglisi, Francesco Maria and Milo, Valerio and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Ossorio, {\´O}scar G. and Wenger, Christian and Pavan, Paolo and Olivo, Piero and Ielmini, Daniele}, title = {Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays}, series = {IEEE Transactions on Electron Devices}, volume = {67}, journal = {IEEE Transactions on Electron Devices}, number = {11}, issn = {0018-9383}, doi = {10.1109/TED.2020.3025271}, pages = {4611 -- 4615}, abstract = {Logic-in-memory (LiM) circuits based on resistive random access memory (RRAM) devices and the material implication logic are promising candidates for the development of low-power computing devices that could fulfill the growing demand of distributed computing systems. However, these circuits are affected by many reliability challenges that arise from device nonidealities (e.g., variability) and the characteristics of the employed circuit architecture. Thus, an accurate investigation of the variability at the array level is needed to evaluate the reliability and performance of such circuit architectures. In this work, we explore the reliability and performance of smart IMPLY (SIMPLY) (i.e., a recently proposed LiM architecture with improved reliability and performance) on two 4-kb RRAM arrays based on different resistive switching oxides integrated in the back end of line (BEOL) of the 0.25- μm BiCMOS process. We analyze the tradeoff between reliability and energy consumption of SIMPLY architecture by exploiting the results of an extensive array-level variability characterization of the two technologies. Finally, we study the worst case performance of a full adder implemented with the SIMPLY architecture and benchmark it on the analogous CMOS implementation.}, language = {en} } @misc{ZahariPerezMahadevaiahetal., author = {Zahari, Finn and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Kohlstedt, Hermann and Wenger, Christian and Ziegler, Martin}, title = {Analogue pattern recognition with stochastic switching binary CMOS‑integrated memristive devices}, series = {Scientific Reports}, volume = {10}, journal = {Scientific Reports}, issn = {2045-2322}, doi = {10.1038/s41598-020-71334-x}, pages = {15}, abstract = {Biological neural networks outperform todays computer technology in terms of power consumption and computing speed when associative tasks, like pattern recognition, are to be solved. The analogue and massive parallel in-memory computing in biology differs strongly with conventional transistor electronics using the von Neumann architecture. Therefore, novel bio-inspired computing architectures are recently highly investigated in the area of neuromorphic computing. Here, memristive devices, which serve as non-volatile resistive memory, are used to emulate the plastic behaviour of biological synapses. In particular, CMOS integrated resistive random access memory (RRAM) devices are promising candidates to extend conventional CMOS technology in neuromorphic systems. However, dealing with the inherent stochasticity of the resistive switching effect can be challenging for network performance. In this work, the probabilistic switching is exploited to emulate stochastic plasticity with fully CMOS integrated binary RRAM devices. Two different RRAM technologies with different device variabilities are investigated in detail and their use in a stochastic artificial neural network (StochANN) to solve the MINST pattern recognition task is examined. A mixed-signal implementation with hardware synapses and software neurons as well as numerical simulations show the proposed concept of stochastic computing is able to handle analogue data with binary memory cells.}, language = {en} } @misc{PerezOssorioDuenasetal., author = {P{\´e}rez, Eduardo and Ossorio, {\´O}scar G. and Due{\~n}as, Salvador and Cast{\´a}n, Helena and Garc{\´i}a, Hector and Wenger, Christian}, title = {Programming Pulse Width Assessment for Reliable and Low-Energy Endurance Performance in Al:HfO2-Based RRAM Arrays}, series = {Electronics (MDPI)}, volume = {9}, journal = {Electronics (MDPI)}, number = {5}, issn = {2079-9292}, doi = {10.3390/electronics9050864}, abstract = {A crucial step in order to achieve fast and low-energy switching operations in resistive random access memory (RRAM) memories is the reduction of the programming pulse width. In this study, the incremental step pulse with verify algorithm (ISPVA) was implemented by using different pulse widths between 10 μ s and 50 ns and assessed on Al-doped HfO 2 4 kbit RRAM memory arrays. The switching stability was assessed by means of an endurance test of 1k cycles. Both conductive levels and voltages needed for switching showed a remarkable good behavior along 1k reset/set cycles regardless the programming pulse width implemented. Nevertheless, the distributions of voltages as well as the amount of energy required to carry out the switching operations were definitely affected by the value of the pulse width. In addition, the data retention was evaluated after the endurance analysis by annealing the RRAM devices at 150 °C along 100 h. Just an almost negligible increase on the rate of degradation of about 1 μ A at the end of the 100 h of annealing was reported between those samples programmed by employing a pulse width of 10 μ s and those employing 50 ns. Finally, an endurance performance of 200k cycles without any degradation was achieved on 128 RRAM devices by using programming pulses of 100 ns width}, language = {en} } @misc{MiloAnzaloneZambellietal., author = {Milo, Valerio and Anzalone, Francesco and Zambelli, Cristian and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Ossorio, {\´O}scar G. and Olivo, Piero and Wenger, Christian and Ielmini, Daniele}, title = {Optimized programming algorithms for multilevel RRAM in hardware neural networks}, series = {IEEE International Reliability Physics Symposium (IRPS), 2021}, journal = {IEEE International Reliability Physics Symposium (IRPS), 2021}, isbn = {978-1-7281-6894-4}, issn = {1938-1891}, doi = {10.1109/IRPS46558.2021.9405119}, abstract = {A key requirement for RRAM in neural network accelerators with a large number of synaptic parameters is the multilevel programming. This is hindered by resistance imprecision due to cycle-to-cycle and device-to-device variations. Here, we compare two multilevel programming algorithms to minimize resistance variations in a 4-kbit array of HfO 2 RRAM. We show that gate-based algorithms have the highest reliability. The optimized scheme is used to implement a neural network with 9-level weights, achieving 91.5\% (vs. software 93.27\%) in MNIST recognition.}, language = {en} } @misc{PetrykDykaPerezetal., author = {Petryk, Dmytro and Dyka, Zoya and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Kabin, Ievgen and Wenger, Christian and Langend{\"o}rfer, Peter}, title = {Evaluation of the Sensitivity of RRAM Cells to Optical Fault Injection Attacks}, series = {EUROMICRO Conference on Digital System Design (DSD 2020), Special Session: Architecture and Hardware for Security Applications (AHSA)}, journal = {EUROMICRO Conference on Digital System Design (DSD 2020), Special Session: Architecture and Hardware for Security Applications (AHSA)}, isbn = {978-1-7281-9535-3}, issn = {978-1-7281-9536-0}, doi = {10.1109/DSD51259.2020.00047}, pages = {8}, language = {en} } @misc{RomeroZalizPerezJimenezMolinosetal., author = {Romero-Zaliz, Roc{\´i}o and P{\´e}rez, Eduardo and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {Influence of variability on the performance of HfO2 memristor-based convolutional neural networks}, series = {Solid State Electronics}, volume = {185}, journal = {Solid State Electronics}, issn = {0038-1101}, doi = {10.1016/j.sse.2021.108064}, pages = {5}, abstract = {A study of convolutional neural networks (CNNs) was performed to analyze the influence of quantization and variability in the network synaptic weights. Different CNNs were considered accounting for the number of convolutional layers, size of the filters in the convolutional layer, number of neurons in the final network layers and different sets of quantization levels. The conductance levels of fabricated 1T1R structures based on HfO2 memristors were considered as reference for four or eight level quantization processes at the inference stage of the CNNs, which were previous trained with the MNIST dataset. We also included the variability of the experimental conductance levels that was found to be Gaussian distributed and was correspondingly modeled for the synaptic weight implementation.}, language = {en} } @misc{OssorioVinuesaGarciaetal., author = {Ossorio, {\´O}scar G. and Vinuesa, Guillermo and Garcia, Hector and Sahelices, Benjamin and Due{\~n}as, Salvador and Cast{\´a}n, Helena and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Wenger, Christian}, title = {Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications}, series = {ECS Transactions}, volume = {102}, journal = {ECS Transactions}, number = {2}, issn = {1938-6737}, doi = {10.1149/10202.0029ecst}, pages = {29 -- 35}, abstract = {The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.}, language = {en} } @misc{BaroniZambelliOlivoetal., author = {Baroni, Andrea and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele}, title = {Tackling the Low Conductance State Drift through Incremental Reset and Verify in RRAM Arrays}, series = {2021 IEEE International Integrated Reliability Workshop (IIRW), South Lake Tahoe, CA, USA, 10 December 2021}, journal = {2021 IEEE International Integrated Reliability Workshop (IIRW), South Lake Tahoe, CA, USA, 10 December 2021}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {978-1-6654-1794-5}, issn = {2374-8036}, doi = {10.1109/IIRW53245.2021.9635613}, pages = {5}, abstract = {Resistive switching memory (RRAM) is a promising technology for highly efficient computing scenarios. RRAM arrays enabled the acceleration of neural networks for artificial intelligence and the creation of In-Memory Computing circuits. However, the arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation in those applications. Among those, one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are fundamental for an accurate Multi-level conductance operation. In this work, we tackle the issue by developing an Incremental Reset and Verify technique showing enhanced variability and reliability features compared with a traditional refresh-based approach.}, language = {en} } @misc{RomeroZalizCantudoPerezetal., author = {Romero-Zaliz, Rocio and Cantudo, Antonio and P{\´e}rez, Eduardo and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {An Analysis on the Architecture and the Size of Quantized Hardware Neural Networks Based on Memristors}, series = {Electronics (MDPI)}, volume = {10}, journal = {Electronics (MDPI)}, number = {24}, issn = {2079-9292}, doi = {10.3390/electronics10243141}, abstract = {We have performed different simulation experiments in relation to hardware neural networks (NN) to analyze the role of the number of synapses for different NN architectures in the network accuracy, considering different datasets. A technology that stands upon 4-kbit 1T1R ReRAM arrays, where resistive switching devices based on HfO2 dielectrics are employed, is taken as a reference. In our study, fully dense (FdNN) and convolutional neural networks (CNN) were considered, where the NN size in terms of the number of synapses and of hidden layer neurons were varied. CNNs work better when the number of synapses to be used is limited. If quantized synaptic weights are included, we observed thatNNaccuracy decreases significantly as the number of synapses is reduced; in this respect, a trade-off between the number of synapses and the NN accuracy has to be achieved. Consequently, the CNN architecture must be carefully designed; in particular, it was noticed that different datasets need specific architectures according to their complexity to achieve good results. It was shown that due to the number of variables that can be changed in the optimization of a NN hardware implementation, a specific solution has to be worked in each case in terms of synaptic weight levels, NN architecture, etc.}, language = {en} } @misc{MannocciBaroniMelacarneetal., author = {Mannocci, Piergiulio and Baroni, Andrea and Melacarne, Enrico and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele}, title = {In-Memory Principal Component Analysis by Crosspoint Array of Rresistive Switching Memory}, series = {IEEE Nanotechnology Magazine}, volume = {16}, journal = {IEEE Nanotechnology Magazine}, number = {2}, issn = {1932-4510}, doi = {10.1109/MNANO.2022.3141515}, pages = {4 -- 13}, abstract = {In Memory Computing (IMC) is one of the most promising candidates for data-intensive computing accelerators of machine learning (ML). A key ML algorithm for dimensionality reduction and classification is principal component analysis (PCA), which heavily relies on matrixvector multiplications (MVM) for which classic von Neumann architectures are not optimized. Here, we provide the experimental demonstration of a new IMCbased PCA algorithm based on power iteration and deflation executed in a 4-kbit array of resistive switching random-access memory (RRAM). The classification accuracy of the Wisconsin Breast Cancer data set reaches 95.43\%, close to floatingpoint implementation. Our simulations indicate a 250× improvement in energy efficiency compared to commercial GPUs, thus supporting IMC for energy-efficient ML in modern data-intensive computing.}, language = {en} } @misc{GlukhovMiloBaronietal., author = {Glukhov, Artem and Milo, Valerio and Baroni, Andrea and Lepri, Nicola and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele}, title = {Statistical model of program/verify algorithms in resistive-switching memories for in-memory neural network accelerators}, series = {2022 IEEE International Reliability Physics Symposium (IRPS)}, journal = {2022 IEEE International Reliability Physics Symposium (IRPS)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {978-1-6654-7950-9}, issn = {2473-2001}, doi = {10.1109/IRPS48227.2022.9764497}, pages = {3C.3-1 -- 3C.3-7}, abstract = {Resistive-switching random access memory (RRAM) is a promising technology for in-memory computing (IMC) to accelerate training and inference of deep neural networks (DNNs). This work presents the first physics-based statistical model describing (i) multilevel RRAM device program/verify (PV) algorithms by controlled set transition, (ii) the stochastic cycle-to-cycle (C2C) and device-to-device (D2D) variations within the array, and (iii) the impact of such imprecisions on the accuracy of DNN accelerators. The model can handle the full chain from RRAM materials/device parameters to the DNN performance, thus providing a valuable tool for device/circuit codesign of hardware DNN accelerators.}, language = {en} } @misc{BaroniGlukhovPerezetal., author = {Baroni, Andrea and Glukhov, Artem and P{\´e}rez, Eduardo and Wenger, Christian and Calore, Enrico and Schifano, Sebastiano Fabio and Olivo, Piero and Ielmini, Daniele and Zambelli, Cristian}, title = {An energy-efficient in-memory computing architecture for survival data analysis based on resistive switching memories}, series = {Frontiers in Neuroscience}, volume = {Vol. 16}, journal = {Frontiers in Neuroscience}, issn = {1662-4548}, doi = {10.3389/fnins.2022.932270}, pages = {1 -- 16}, abstract = {One of the objectives fostered in medical science is the so-called precision medicine, which requires the analysis of a large amount of survival data from patients to deeply understand treatment options. Tools like Machine Learning and Deep Neural Networks are becoming a de-facto standard. Nowadays, computing facilities based on the Von Neumann architecture are devoted to these tasks, yet rapidly hitting a bottleneck in performance and energy efficiency. The In-Memory Computing (IMC) architecture emerged as a revolutionary approach to overcome that issue. In this work, we propose an IMC architecture based on Resistive switching memory (RRAM) crossbar arrays to provide a convenient primitive for matrix-vector multiplication in a single computational step. This opens massive performance improvement in the acceleration of a neural network that is frequently used in survival analysis of biomedical records, namely the DeepSurv. We explored how the synaptic weights mapping strategy and the programming algorithms developed to counter RRAM non-idealities expose a performance/energy trade-off. Finally, we assessed the benefits of the proposed architectures with respect to a GPU-based realization of the same task, evidencing a tenfold improvement in terms of performance and three orders of magnitude with respect to energy efficiency.}, language = {en} } @misc{BaroniGlukhovPerezetal., author = {Baroni, Andrea and Glukhov, Artem and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele and Olivo, Piero and Zambelli, Cristian}, title = {Low Conductance State Drift Characterization and Mitigation in Resistive Switching Memories (RRAM) for Artificial Neural Networks}, series = {IEEE Transactions on Device and Materials Reliability}, volume = {22}, journal = {IEEE Transactions on Device and Materials Reliability}, number = {3}, issn = {1530-4388}, doi = {10.1109/TDMR.2022.3182133}, pages = {340 -- 347}, abstract = {The crossbar structure of Resistive-switching random access memory (RRAM) arrays enabled the In-Memory Computing circuits paradigm, since they imply the native acceleration of a crucial operations in this scenario, namely the Matrix-Vector-Multiplication (MVM). However, RRAM arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation. A critical one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are mandatory for an accurate multi-level conductance operation. In this work, we analyze the benefits of a new programming algorithm that embodies Set and Reset switching operations to achieve better conductance control and lower variability. Data retention analysis performed with different temperatures for 168 hours evidence its superior performance with respect to standard programming approach. Finally, we explored the benefits of using our methodology at a higher abstraction level, through the simulation of an Artificial Neural Network for image recognition task (MNIST dataset). The accuracy achieved shows higher performance stability over temperature and time.}, language = {en} } @misc{GlukhovLepriMiloetal., author = {Glukhov, Artem and Lepri, Nicola and Milo, Valerio and Baroni, Andrea and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele}, title = {End-to-end modeling of variability-aware neural networks based on resistive-switching memory arrays}, series = {Proc. 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2022)}, journal = {Proc. 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2022)}, doi = {10.1109/VLSI-SoC54400.2022.9939653}, pages = {1 -- 5}, abstract = {Resistive-switching random access memory (RRAM) is a promising technology that enables advanced applications in the field of in-memory computing (IMC). By operating the memory array in the analogue domain, RRAM-based IMC architectures can dramatically improve the energy efficiency of deep neural networks (DNNs). However, achieving a high inference accuracy is challenged by significant variation of RRAM conductance levels, which can be compensated by (i) advanced programming techniques and (ii) variability-aware training (VAT) algorithms. In both cases, however, detailed knowledge and accurate physics-based statistical models of RRAM are needed to develop programming and VAT methodologies. This work presents an end-to-end approach to the development of highly-accurate IMC circuits with RRAM, encompassing the device modeling, the precise programming algorithm, and the VAT simulations to maximize the DNN classification accuracy in presence of conductance variations.}, language = {en} } @misc{WenBaroniPerezetal., author = {Wen, Jianan and Baroni, Andrea and P{\´e}rez, Eduardo and Ulbricht, Markus and Wenger, Christian and Krstic, Milos}, title = {Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages}, series = {2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, journal = {2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, isbn = {978-1-6654-5938-9}, issn = {2765-933X}, doi = {10.1109/DFT56152.2022.9962345}, pages = {1 -- 6}, abstract = {RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel states.}, language = {en} } @misc{PechmannPerezWengeretal., author = {Pechmann, Stefan and P{\´e}rez, Eduardo and Wenger, Christian and Hagelauer, Amelie}, title = {A current mirror Based read circuit design with multi-level capability for resistive switching deviceb}, series = {2024 International Conference on Electronics, Information, and Communication (ICEIC)}, journal = {2024 International Conference on Electronics, Information, and Communication (ICEIC)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-7188-8}, issn = {2767-7699}, doi = {10.1109/ICEIC61013.2024.10457188}, pages = {4}, abstract = {This paper presents a read circuit design for resistive memory cells based on current mirrors. The circuit utilizes high-precision current mirrors and reference cells to determine the state of resistive memory using comparators. It offers a high degree in adaptability in terms of both resistance range and number of levels. Special emphasis was put on device protection to prevent accidental programming of the memory during read operations. The realized circuit can resolve eight states with a resolution of up to 1 k Ω, realizing a digitization of the analog memory information. Furthermore, the integration in a complete memory macro is shown. The circuit was realized in a 130 nm-process but can easily be adapted to other processes and resistive memory technologies.}, language = {en} } @misc{NikiruyPerezBaronietal., author = {Nikiruy, Kristina and P{\´e}rez, Eduardo and Baroni, Andrea and Dorai Swamy Reddy, Keerthi and Pechmann, Stefan and Wenger, Christian and Ziegler, Martin}, title = {Blooming and pruning: learning from mistakes with memristive synapses}, series = {Scientific Reports}, volume = {14}, journal = {Scientific Reports}, number = {1}, issn = {2045-2322}, doi = {10.1038/s41598-024-57660-4}, abstract = {AbstractBlooming and pruning is one of the most important developmental mechanisms of the biological brain in the first years of life, enabling it to adapt its network structure to the demands of the environment. The mechanism is thought to be fundamental for the development of cognitive skills. Inspired by this, Chialvo and Bak proposed in 1999 a learning scheme that learns from mistakes by eliminating from the initial surplus of synaptic connections those that lead to an undesirable outcome. Here, this idea is implemented in a neuromorphic circuit scheme using CMOS integrated HfO2-based memristive devices. The implemented two-layer neural network learns in a self-organized manner without positive reinforcement and exploits the inherent variability of the memristive devices. This approach provides hardware, local, and energy-efficient learning. A combined experimental and simulation-based parameter study is presented to find the relevant system and device parameters leading to a compact and robust memristive neuromorphic circuit that can handle association tasks.}, language = {en} } @inproceedings{WenVargasZhuetal., author = {Wen, Jianan and Vargas, Fabian Luis and Zhu, Fukun and Reiser, Daniel and Baroni, Andrea and Fritscher, Markus and P{\´e}rez, Eduardo and Reichenbach, Marc and Wenger, Christian and Krstic, Milos}, title = {Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment}, series = {2024 IEEE 25th Latin American Test Symposium (LATS)}, booktitle = {2024 IEEE 25th Latin American Test Symposium (LATS)}, publisher = {IEEE}, doi = {10.1109/LATS62223.2024.10534601}, pages = {6}, abstract = {Emerging device technologies such as resistive RAM (RRAM) are increasingly recognized in enhancing system performance, particularly in applications demanding extensive vector-matrix multiplications (VMMs) with high parallelism. However, a significant limitation in current electronics design automation (EDA) tools is their lack of support for rapid prototyping, design space exploration, and the integration of inherent process-dependent device variability into system-level simulations, which is essential for assessing system reliability. To address this gap, we introduce a field-programmable gate array (FPGA) based emulation approach for RRAM crossbars featuring cycle-accurate emulations in real time without relying on complex device models. Our approach is based on pre-generated look-up tables (LUTs) to accurately represent the RRAM device behavior. To efficiently model the device variability at the system level, we propose using the multivariate kernel density estimation (KDE) method to augment the measured RRAM data. The proposed emulator allows precise latency determination for matrix mapping and computation operations. Meanwhile, by coupling with the NeuroSim framework, the corresponding energy consumption can be estimated. In addition to facilitating a range of in-depth system assessments, experimental results suggest a remarkable reduction of emulation time compared to the classic behavioral simulation.}, language = {en} } @misc{DoraiSwamyReddyPerezBaronietal., author = {Dorai Swamy Reddy, Keerthi and P{\´e}rez, Eduardo and Baroni, Andrea and Mahadevaiah, Mamathamba Kalishettyhalli and Marschmeyer, Steffen and Fraschke, Mirko and Lisker, Marco and Wenger, Christian and Mai, Andreas}, title = {Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance}, series = {The European Physical Journal B}, volume = {97}, journal = {The European Physical Journal B}, publisher = {Springer Science and Business Media LLC}, issn = {1434-6028}, doi = {10.1140/epjb/s10051-024-00821-1}, pages = {9}, abstract = {Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal-insulator-metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2 dielectric thickness from 8 nm to 5 nm. Additionally, 5\% Al-doped 4 nm HfO2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology.}, language = {en} } @misc{MaldonadoCantudoSwamyReddyetal., author = {Maldonado, David and Cantudo, Antonio and Swamy Reddy, Keerthi Dorai and Pechmann, Stefan and Uhlmann, Max and Wenger, Christian and Roldan, Juan Bautista and P{\´e}rez, Eduardo}, title = {Influence of stop and gate voltage on resistive switching of 1T1R HfO2-based memristors, a modeling and variability analysis}, series = {Materials Science in Semiconductor Processing}, volume = {182}, journal = {Materials Science in Semiconductor Processing}, issn = {1873-4081}, doi = {10.1016/j.mssp.2024.108726}, pages = {9}, language = {en} } @misc{VinuesaGarciaPerezetal., author = {Vinuesa, Guillermo and Garc{\´i}a, H{\´e}ctor and P{\´e}rez, Eduardo and Wenger, Christian and {\´I}{\~n}iguez de la Torre, Ignacio and Gonz{\´a}lez, Tom{\´a}s and Due{\~n}as, Salvador and Cast{\´a}n, Helena}, title = {On the asymmetry of Resistive Switching Transitions}, series = {Electronics}, volume = {13}, journal = {Electronics}, number = {13}, publisher = {MDPI}, issn = {2079-9292}, doi = {10.3390/electronics13132639}, pages = {11}, abstract = {In this study, the resistive switching phenomena in TiN/Ti/HfO2/Ti metal-insulator-metal stacks is investigated, mainly focusing on the analysis of set and reset transitions. The electrical measurements in a wide temperature range reveal that the switching transitions require less voltage (and thus, less energy) as temperature rises, with the reset process being much more temperature sensitive. The main conduction mechanism in both resistance states is Space-charge-limited Conduction, but the high conductivity state also shows Schottky emission, explaining its temperature dependence. Moreover, the temporal evolution of these transitions reveals clear differences between them, as their current transient response is completely different. While the set is sudden, the reset process development is clearly non-linear, closely resembling a sigmoid function. This asymmetry between switching processes is of extreme importance in the manipulation and control of the multi-level characteristics and has clear implications in the possible applications of resistive switching devices in neuromorphic computing.}, language = {en} } @misc{VinuesaGarciaDuenasetal., author = {Vinuesa, Guillermo and Garcia, Hector and Duenas, Salvador and Castan, Helena and I{\~n}iguez de la Torre, Ignacio and Gonzalez, Tomas and Dorai Swamy Reddy, Keerthi and Uhlmann, Max and Wenger, Christian and Perez, Eduardo}, title = {Effect of the temperature on the performance and dynamic behavior of HfO2-Based Rram Devices}, series = {ECS Meeting Abstracts}, volume = {MA2024-01}, journal = {ECS Meeting Abstracts}, number = {21}, publisher = {The Electrochemical Society}, issn = {2151-2043}, doi = {10.1149/MA2024-01211297mtgabs}, pages = {1297 -- 1297}, abstract = {Over the past decades, the demand for semiconductor memory devices has been steadily increasing, and is currently experiencing an unprecedented boost due to the development and expansion of artificial intelligence. Among emerging high-density non-volatile memories, resistive random-access memory (RRAM) is one of the best recourses for all kind of applications, such as neuromorphic computing or hardware security [1]. Although many materials have been evaluated for RRAM development, some of them with excellent results, HfO2 is one of the established materials in CMOS domain due to its compatibility with standard materials and processes [2]. The main goal of this work is to study the switching capability and stability of HfO2-based RRAMs, as well as to explore their ability in the field of analogue applications, by analyzing the evolution of the resistance states that allow multilevel control. Indeed, analogue operation is a key point for achieving electronic neural synapses in neuromorphic systems, with synaptic weight information encoded in the different resistance states. This research has been carried out over a wide temperature range, between 40 and 340 K, as we are interested in testing the extent to which performance is maintained or modified, with a view to designing neuromorphic circuits that are also suitable in the low-temperature realm. We aim to prove that these simple, fast, high integration density structures can also be used in circuits designed for specific applications, such as aerospace systems. The RRAM devices studied in this work are TiN/Ti/8 nm-HfO2/TiN metal-insulator-metal (MIM) capacitors. Dielectric layers were atomic layer deposited (ALD). It has been demonstrated that the Ti coat in the top electrode acts as a scavenger that absorbs oxygen atoms from the HfO2 layer, and facilitates the creation of conductive filaments of oxygen vacancies [3]. In fact, the oxygen reservoir capability of Ti is well known, as it is able to attract and release oxygen atoms from or to the HfO2 layer during the RRAM operation [4]. The clustering of vacancies extends through the entire thickness of the oxide and, after an electroformig step, it joins the upper and lower electrodes and the device reaches the low resistance state (LRS). By applying adequate electrical signals, the filaments can be partially dissolved, which brings the device into the high-resistance state (HRS), with lower current values. The set process brings the device to the LRS state, while the reset one brings it to the HRS. The dependence of electrical conductivity on external applied electrical excitation allows triggering the device between the both states in a non-volatile manner [5]. The experimental equipment used consisted of a Keithley 4200-SCS semiconductor parameter analyzer and a Lake Shore cryogenic probe station. Fig.1 shows current-voltage cycles measured at different temperatures; the averages values at each temperature, both in logarithmic and linear scale, are also shown. The functional window increases as temperature decreases. The evolutions of set and reset voltage values with temperature are depicted in Fig.2, whereas the current values (measured at 0.1 V) corresponding to the LRS and HRS can be seen in Fig.3. LRS resistance decreases as temperature increases, in agreement with semiconductor behaviour, probably due to a hopping conduction mechanism. Both set and reset voltages decrease as temperature increases; the reset process is smoother at high temperatures. The reduction in reset voltage variability as temperature increases is very notable. Finally, Fig. 4 shows a picture of the transient behaviour; in the right panel of the same figure, the amplitudes of the current transients in the reset state have been included in the external loop. To sum up, the resistive switching phenomena is studied in a wide temperature range. The LRS shows semiconducting behavior with temperature, most likely related to a hopping conduction mechanism. Switching voltages decrease as temperature increases, with a notable reduction in reset voltage variability. An excellent control of intermediate resistance state is shown through current transients at several voltages in the reset process. REFERENCES [1] M. Asif et al., Materials Today Electronics 1, 100004 (2022). [2] S. Slesazeck et al., Nanotechnology 30, 352003 (2019). [3] Z. Fang et al., IEEE Electron Device Letters 35, 9, 912-914 (2014). [4] H. Y. Lee et al., IEEE Electron Device Letters 31, 1, 44-46 (2010). [5] D. J. Wouters et al., Proceedings of the IEEE 103, 8, 1274-1288 (2015). Figure 1}, language = {en} } @misc{DerschRoemerPerezetal., author = {Dersch, Nadine and Roemer, Christian and Perez, Eduardo and Wenger, Christian and Schwarz, Mike and I{\~n}{\´i}guez, Benjam{\´i}n and Kloes, Alexander}, title = {Fast circuit simulation of memristive crossbar arrays with bimodal stochastic synaptic weights}, series = {2024 IEEE Latin American Electron Devices Conference (LAEDC)}, journal = {2024 IEEE Latin American Electron Devices Conference (LAEDC)}, publisher = {IEEE}, isbn = {979-8-3503-6130-8}, issn = {979-8-3503-6129-2}, doi = {10.1109/LAEDC61552.2024.10555829}, pages = {1 -- 4}, abstract = {This paper presents an approach for highly efficient circuit simulation of hardware-based artificial neural networks by using memristive crossbar array architectures. There are already possibilities to test neural networks with stochastic weights via simulations like the macro model NeuroSim. However, the noise-based variability approach offers more realistic setting options including elements of a classical circuit simulation for more precise analysis of neural networks. With this approach, statistical parameter fluctuations can be simulated based on different distribution functions of devices. In Cadence Virtuoso, a simulation of a crossbar array with 10 synaptic weights following a bimodal distribution, the new approach shows a 1,000x speedup compared to a Monte Carlo simulation. Initial tests of a memristive crossbar array with over 15,000 stochastic weights to classify the MNIST dataset show that the new approach can be used to test the functionality of hardware-based neural networks.}, language = {en} } @misc{WenBaroniPerezetal., author = {Wen, Jianan and Baroni, Andrea and Perez, Eduardo and Uhlmann, Max and Fritscher, Markus and KrishneGowda, Karthik and Ulbricht, Markus and Wenger, Christian and Krstic, Milos}, title = {Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator}, series = {2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}, journal = {2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}, publisher = {IEEE}, isbn = {978-3-9819263-8-5}, issn = {1558-1101}, doi = {10.23919/DATE58400.2024.10546709}, pages = {1 -- 6}, abstract = {The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 \% and 18 \%, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83\% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero.}, language = {en} } @misc{MaldonadoBaroniAldanaetal., author = {Maldonado, David and Baroni, Andrea and Aldana, Samuel and Dorai Swamy Reddy, Keerthi and Pechmann, Stefan and Wenger, Christian and Rold{\´a}n, Juan Bautista and P{\´e}rez, Eduardo}, title = {Kinetic Monte Carlo simulation analysis of the conductance drift in Multilevel HfO2-based RRAM devices}, series = {Nanoscale}, volume = {16}, journal = {Nanoscale}, number = {40}, publisher = {Royal Society of Chemistry (RSC)}, issn = {2040-3364}, doi = {10.1039/d4nr02975e}, pages = {19021 -- 19033}, abstract = {The drift characteristics of valence change memory (VCM) devices have been analyzed through both experimental analysis and 3D kinetic Monte Carlo (kMC) simulations.}, language = {en} } @misc{PetrykDykaPerezetal., author = {Petryk, Dmytro and Dyka, Zoya and P{\´e}rez, Eduardo and Kabin, Ievgen and Katzer, Jens and Sch{\"a}ffner, Jan and Langend{\"o}rfer, Peter}, title = {Sensitivity of HfO2-based RRAM Cells to Laser Irradiation}, series = {Microprocessors and Microsystems}, journal = {Microprocessors and Microsystems}, number = {87}, issn = {0141-9331}, doi = {10.1016/j.micpro.2021.104376}, language = {en} } @misc{WenVargasZhuetal., author = {Wen, Jianan and Vargas, Fabian Luis and Zhu, Fukun and Reiser, Daniel and Baroni, Andrea and Fritscher, Markus and Perez, Eduardo and Reichenbach, Marc and Wenger, Christian and Krstic, Milos}, title = {RRAMulator : an efficient FPGA-based emulator for RRAM crossbar with device variability and energy consumption evaluation}, series = {Microelectronics Reliability}, volume = {168}, journal = {Microelectronics Reliability}, publisher = {Elsevier BV}, address = {Amsterdam}, issn = {0026-2714}, doi = {10.1016/j.microrel.2025.115630}, pages = {1 -- 10}, abstract = {The in-memory computing (IMC) systems based on emerging technologies have gained significant attention due to their potential to enhance performance and energy efficiency by minimizing data movement between memory and processing unit, which is especially beneficial for data-intensive applications. Designing and evaluating systems utilizing emerging memory technologies, such as resistive RAM (RRAM), poses considerable challenges due to the limited support from electronics design automation (EDA) tools for rapid development and design space exploration. Additionally, incorporating technology-dependent variability into system-level simulations is critical to accurately assess the impact on system reliability and performance. To bridge this gap, we propose RRAMulator, a field-programmable gate array (FPGA) based hardware emulator for RRAM crossbar array. To avoid the complex device models capturing the nonlinear current-voltage (IV) relationships that degrade emulation speed and increase hardware utilization, we propose a device and variability modeling approach based on device measurements. We deploy look-up tables (LUTs) for device modeling and use the multivariate kernel density estimation (KDE) method to augment existing data, extending data variety and avoiding repetitive data usage. The proposed emulator achieves cycle-accurate, real-time emulations and provides information such as latency and energy consumption for matrix mapping and vector-matrix multiplications (VMMs). Experimental results show a significant reduction in emulation time compared to conventional behavioral simulations. Additionally, an RRAM-based discrete Fourier transform (DFT) accelerator is analyzed as a case study featuring a range of in-depth system assessments.}, language = {en} } @misc{UhlmannKrysikWenetal., author = {Uhlmann, Max and Krysik, Milosz and Wen, Jianan and Frohberg, Max and Baroni, Andrea and Reddy, Keerthi Dorai Swamy and P{\´e}rez, Eduardo and Ostrovskyy, Philip and Piotrowski, Krzysztof and Carta, Corrado and Wenger, Christian and Kahmen, Gerhard}, title = {A compact one-transistor-multiple-RRAM characterization platform}, series = {IEEE transactions on circuits and systems I : regular papers}, journal = {IEEE transactions on circuits and systems I : regular papers}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {1549-8328}, doi = {10.1109/TCSI.2025.3555234}, pages = {1 -- 12}, abstract = {Emerging non-volatile memories (eNVMs) such as resistive random-access memory (RRAM) offer an alternative solution compared to standard CMOS technologies for implementation of in-memory computing (IMC) units used in artificial neural network (ANN) applications. Existing measurement equipment for device characterisation and programming of such eNVMs are usually bulky and expensive. In this work, we present a compact size characterization platform for RRAM devices, including a custom programming unit IC that occupies less than 1 mm2 of silicon area. Our platform is capable of testing one-transistor-one-RRAM (1T1R) as well as one-transistor-multiple-RRAM (1TNR) cells. Thus, to the best knowledge of the authors, this is the first demonstration of an integrated programming interface for 1TNR cells. The 1T2R IMC cells were fabricated in the IHP's 130 nm BiCMOS technology and, in combination with other parts of the platform, are able to provide more synaptic weight resolution for ANN model applications while simultaneously decreasing the energy consumption by 50 \%. The platform can generate programming voltage pulses with a 3.3 mV accuracy. Using the incremental step pulse with verify algorithm (ISPVA) we achieve 5 non-overlapping resistive states per 1T1R device. Based on those 1T1R base states we measure 15 resulting state combinations in the 1T2R cells.}, language = {en} } @misc{BaroniPerezReddyetal., author = {Baroni, Andrea and P{\´e}rez, Eduardo and Reddy, Keerthi Dorai Swamy and Pechmann, Stefan and Wenger, Christian and Ielmini, Daniele and Zambelli, Cristian}, title = {Enhancing RRAM reliability : exploring the effects of Al doping on HfO2-based devices}, series = {IEEE transactions on device and materials reliability}, journal = {IEEE transactions on device and materials reliability}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {1530-4388}, doi = {10.1109/TDMR.2025.3581061}, pages = {1 -- 9}, abstract = {This study provides a comprehensive evaluation of RRAM devices based on HfO2 and Al-doped HfO2 insulators, focusing on critical performance metrics, including Forming yield, Post-Programming Stability (PPS), Fast Drift, Endurance, and Retention at elevated temperatures (125 ∘C). Aluminum doping significantly enhances device reliability and stability, improving Forming yield, reducing current drift during programming and Retention tests, and minimizing variability during Endurance cycling. While Al5\%:HfO2 achieves most of the observed benefits compared to pure HfO2, Al7\%:HfO2 offers incremental advantages for scenarios requiring extreme reliability. These findings position Al-doped HfO2 devices as a promising solution for RRAM-based systems in memory and neuromorphic computing, highlighting the potential trade-off between performance gains and increased fabrication complexity. This work underlines the importance of material engineering for optimizing RRAM devices in application-specific contexts.}, language = {en} } @misc{BlumensteinPerezWengeretal., author = {Blumenstein, Alan and P{\´e}rez, Eduardo and Wenger, Christian and Dersch, Nadine and Kloes, Alexander and I{\~n}{\´i}guez, Benjam{\´i}n and Schwarz, Mike}, title = {Evaluating device variability in RRAM-based single- and multi-layer perceptrons}, series = {2025 32nd International Conference on Mixed Design of Integrated Circuits and System (MIXDES)}, journal = {2025 32nd International Conference on Mixed Design of Integrated Circuits and System (MIXDES)}, publisher = {IEEE}, address = {New York}, isbn = {978-83-63578-27-5}, doi = {10.23919/MIXDES66264.2025.11092102}, pages = {74 -- 77}, abstract = {This work investigates the impact of stochastic weight variations in hardware implementations of artificial neural networks, focusing on a Single-Layer Perceptron and Multi-Layer Perceptrons. A variable neural network model is introduced, applying Gaussian variability to synaptic weights based on an adjustment rate, which controls the proportion of affected weights. By studying how stochastic variations affect accuracy, simulations under device-to-device and cycle-to-cycle variation conditions demonstrate that Single-Layer Perceptrons are more sensitive to weight variations, while Multi-Layer perceptrons show greater robustness. Additionally, stochastic quantization improves the performance of Multi-Layer Perceptrons but has minimal effect on Single-Layer Perceptrons.}, language = {en} } @misc{WenBaroniUhlmannetal., author = {Wen, Jianan and Baroni, Andrea and Uhlmann, Max and Perez, Eduardo and Wenger, Christian and Krstic, Milos}, title = {ReFFT : an energy-efficient RRAM-based FFT accelerator}, series = {IEEE transactions on computer-aided design of integrated circuits and systems}, journal = {IEEE transactions on computer-aided design of integrated circuits and systems}, publisher = {IEEE}, address = {Piscataway, NJ}, issn = {0278-0070}, doi = {10.1109/TCAD.2025.3627146}, pages = {1 -- 14}, abstract = {The fast Fourier transform (FFT) is a highly efficient algorithm for computing the discrete Fourier transform (DFT). It is widely employed in various applications, including digital communication, image processing, and signal analysis. Recently, in-memory computing architectures based on emerging technologies, such as resistive RAM (RRAM), have demonstrated promising performance with low hardware cost for data-intensive applications. However, directly mapping FFT onto RRAM crossbars is challenging because the algorithm relies on many small, sequential butterfly operations, while cross-bars are optimized for large-scale, highly parallel vector-matrix multiplications (VMMs). In this paper, we introduce ReFFT, a system architecture that reformulates FFT computations for efficient execution on RRAM crossbars. ReFFT combines the reduced computational complexity of FFT with the parallel VMM capability of RRAM. We incorporate measured device data into our framework to analyze the effect of variability and develop an adaptive mapping scheme that improves twiddle-factor programming accuracy, leading to a 9.9 dB peak signal-to-noise ratio (PSNR) improvement for a 256-point FFT. Compared with prior RRAM-based DFT designs, ReFFT achieves up to 4.6× and 19.5× higher energy efficiency for 256- and 2048-point FFTs, respectively. The system is further validated in digital communication and satellite image compression tasks.}, language = {en} } @misc{DerschPerezWengeretal., author = {Dersch, Nadine and Perez, Eduardo and Wenger, Christian and Lanza, Mario and Zhu, Kaichen and Schwarz, Mike and I{\~n}{\´i}guez, Benjam{\´i}n and Kloes, Alexander}, title = {Statistical model for the calculation of conductance variations of memristive devices}, series = {2025 IEEE European Solid-State Electronics Research Conference (ESSERC)}, journal = {2025 IEEE European Solid-State Electronics Research Conference (ESSERC)}, publisher = {IEEE}, address = {Piscataway, NJ}, doi = {10.1109/ESSERC66193.2025.11213973}, pages = {373 -- 376}, abstract = {This paper presents a statistical model which calculates the expected conductance variations from device to device or from cycle to cycle of memristive devices. The mean readout current and its standard deviation can be calculated for binary and multi-level devices. These values are important for simulating hardware-based artificial neural networks at circuit level and testing their functionality. Research into hardwarebased artificial neural networks is important because they are energy-efficient. Furthermore to calculating the variations, the statistical model can be used to determine what influence the cumulative distribution function of switching has on the variations and which behavior provides the best results for the hardwarebased artificial neural network. Some memristive devices exhibit multi-level behavior due to defects in the switching layer. The number of these defects and the optimal amount can be estimated.}, language = {en} } @misc{DerschPerezWengeretal., author = {Dersch, Nadine and Perez, Eduardo and Wenger, Christian and Schwarz, Mike and Iniguez, Benjamin and Kloes, Alexander}, title = {A closed-form model for programming of oxide-based resistive random access memory cells derived from the Stanford model}, series = {Solid-state electronics}, volume = {230}, journal = {Solid-state electronics}, publisher = {Elsevier BV}, address = {Amsterdam}, issn = {0038-1101}, doi = {10.1016/j.sse.2025.109238}, pages = {1 -- 5}, abstract = {This paper presents a closed-form model for pulse-based programming of oxide-based resistive random access memory devices. The Stanford model is used as a basis and solved in a closed-form for the programming cycle. A constant temperature is set for this solution. With the closed-form model, the state of the device after programming or the required programming settings for achieving a specific device conductance can be calculated directly and quickly. The Stanford model requires time-consuming iterative calculations for high accuracy in transient analysis, which is not necessary for the closed-form model. The closed-form model is scalable across different programming pulse widths and voltages.}, language = {en} } @misc{WenBaroniMistronietal., author = {Wen, Jianan and Baroni, Andrea and Mistroni, Alberto and Perez, Eduardo and Zambelli, Cristian and Wenger, Christian and Krstic, Milos and Bolzani P{\"o}hls, Leticia Maria}, title = {ReDiM : an efficient strategy for read disturb mitigation in RRAM-based accelerators}, series = {2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS)}, journal = {2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS)}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {979-8-3315-3334-2}, doi = {10.1109/IOLTS65288.2025.11117065}, pages = {1 -- 7}, abstract = {Resistive RAM (RRAM) has emerged as a promising non-volatile memory technology for implementing energy-efficient hardware accelerators within the in-memory computing (IMC) paradigm. However, due to the immature fabrication process and inherent material instabilities, frequent read operations during computations can induce read disturb effects, leading to unintended resistance drift and potential data corruption. Existing mitigation approaches primarily focus on detecting read disturb effects and triggering memory refresh operations. In this work, we propose an architecture-level solution that mitigates read disturb in RRAM-based accelerators. Our strategy employs crossbar duplication and decomposes the single high input pulse into two lower-amplitude pulses, effectively minimizing the risk of read disturb. To validate our approach, we develop a simulation framework that incorporates measurement data from characterized RRAM devices under read disturb stress conditions. Experimental results on VGG-8 with CIFAR-10 demonstrate that the proposed method significantly mitigates inference accuracy degradation caused by read disturb in RRAM-based accelerators, while incurring modest area and energy overheads of 12.32\% and 2.15\%, respectively. This work provides a practical and scalable solution for enhancing the robustness of RRAM-based accelerators in edge and high-performance computing applications.}, language = {en} } @misc{BlumensteinPerezWengeretal., author = {Blumenstein, Alan and P{\´e}rez, Eduardo and Wenger, Christian and Dersch, Nadine and Kloes, Alexander and I{\~n}{\´i}guez, Benjam{\´i}n and Schwarz, Mike}, title = {Exploring variability and quantization effects in artificial neural networks using the MNIST dataset}, series = {Solid-state electronics}, volume = {232}, journal = {Solid-state electronics}, publisher = {Elsevier BV}, address = {Amsterdam}, issn = {0038-1101}, doi = {10.1016/j.sse.2025.109296}, pages = {1 -- 4}, abstract = {This paper investigates the impact of introducing variability to trained neural networks and examines the effects of variability and quantization on network accuracy. The study utilizes the MNIST dataset to evaluate various Multi-Layer Perceptron configurations: a baseline model with a Single-Layer Perceptron and an extended model with multiple hidden nodes. The effects of Cycle-to-Cycle variability on network accuracy are explored by varying parameters such as the standard deviation to simulate dynamic changes in network weights. In particular, the performance differences between the Single-Layer Perceptron and the Multi-Layer Perceptron with hidden layers are analyzed, highlighting the network's robustness to stochastic perturbations. These results provide insights into the effects of quantization and network architecture on accuracy under varying levels of variability.}, language = {en} } @misc{PerezMaldonadoPechmannetal., author = {Perez, Eduardo and Maldonado, David and Pechmann, Stefan and Reddy, Keerthi Dorai Swamy and Uhlmann, Max and Hagelauer, Amelie and Roldan, Juan Bautista and Wenger, Christian}, title = {Impact of the series resistance on switching characteristics of 1T1R HfO₂-based RRAM devices}, series = {2025 15th Spanish Conference on Electron Devices (CDE)}, journal = {2025 15th Spanish Conference on Electron Devices (CDE)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {Piscataway, NJ}, isbn = {979-8-3315-9618-7}, doi = {10.1109/CDE66381.2025.11038868}, pages = {1 -- 4}, abstract = {This study investigates the influence of the series resistance (RS) on the switching characteristics of 1-transistor-1-resistor (1T1R) RRAM devices based on HfO2 and Al:HfO₂ dielectrics. Intrinsic RS values were extracted from I-V characteristics measured over 50 Reset-Set cycles at various gate voltages (VG) by using a numerical transformation method. Results reveal the contribution of the transistor's resistance to the overall RS. A linear relationship between RS values and Set transition voltages (VTS) was found, with larger RS values amplifying the variability in switching parameters. Comparative analysis of cumulative distribution functions (CDFs) highlights differences between technologies, showing lower VTS values as well as lower sensitivity to RS for Al:HfO₂-based devices. These findings underscore the critical role of RS in modeling and optimizing the performance of RRAM devices for reliable operation.}, language = {en} }