@misc{OssorioVinuesaGarciaetal., author = {Ossorio, {\´O}scar G. and Vinuesa, Guillermo and Garcia, Hector and Sahelices, Benjamin and Due{\~n}as, Salvador and Cast{\´a}n, Helena and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Wenger, Christian}, title = {Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications}, series = {ECS Transactions}, volume = {102}, journal = {ECS Transactions}, number = {2}, issn = {1938-6737}, doi = {10.1149/10202.0029ecst}, pages = {29 -- 35}, abstract = {The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.}, language = {en} } @misc{BaroniZambelliOlivoetal., author = {Baroni, Andrea and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele}, title = {Tackling the Low Conductance State Drift through Incremental Reset and Verify in RRAM Arrays}, series = {2021 IEEE International Integrated Reliability Workshop (IIRW), South Lake Tahoe, CA, USA, 10 December 2021}, journal = {2021 IEEE International Integrated Reliability Workshop (IIRW), South Lake Tahoe, CA, USA, 10 December 2021}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {978-1-6654-1794-5}, issn = {2374-8036}, doi = {10.1109/IIRW53245.2021.9635613}, pages = {5}, abstract = {Resistive switching memory (RRAM) is a promising technology for highly efficient computing scenarios. RRAM arrays enabled the acceleration of neural networks for artificial intelligence and the creation of In-Memory Computing circuits. However, the arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation in those applications. Among those, one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are fundamental for an accurate Multi-level conductance operation. In this work, we tackle the issue by developing an Incremental Reset and Verify technique showing enhanced variability and reliability features compared with a traditional refresh-based approach.}, language = {en} } @misc{RomeroZalizCantudoPerezetal., author = {Romero-Zaliz, Rocio and Cantudo, Antonio and P{\´e}rez, Eduardo and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {An Analysis on the Architecture and the Size of Quantized Hardware Neural Networks Based on Memristors}, series = {Electronics (MDPI)}, volume = {10}, journal = {Electronics (MDPI)}, number = {24}, issn = {2079-9292}, doi = {10.3390/electronics10243141}, abstract = {We have performed different simulation experiments in relation to hardware neural networks (NN) to analyze the role of the number of synapses for different NN architectures in the network accuracy, considering different datasets. A technology that stands upon 4-kbit 1T1R ReRAM arrays, where resistive switching devices based on HfO2 dielectrics are employed, is taken as a reference. In our study, fully dense (FdNN) and convolutional neural networks (CNN) were considered, where the NN size in terms of the number of synapses and of hidden layer neurons were varied. CNNs work better when the number of synapses to be used is limited. If quantized synaptic weights are included, we observed thatNNaccuracy decreases significantly as the number of synapses is reduced; in this respect, a trade-off between the number of synapses and the NN accuracy has to be achieved. Consequently, the CNN architecture must be carefully designed; in particular, it was noticed that different datasets need specific architectures according to their complexity to achieve good results. It was shown that due to the number of variables that can be changed in the optimization of a NN hardware implementation, a specific solution has to be worked in each case in terms of synaptic weight levels, NN architecture, etc.}, language = {en} } @misc{MannocciBaroniMelacarneetal., author = {Mannocci, Piergiulio and Baroni, Andrea and Melacarne, Enrico and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele}, title = {In-Memory Principal Component Analysis by Crosspoint Array of Rresistive Switching Memory}, series = {IEEE Nanotechnology Magazine}, volume = {16}, journal = {IEEE Nanotechnology Magazine}, number = {2}, issn = {1932-4510}, doi = {10.1109/MNANO.2022.3141515}, pages = {4 -- 13}, abstract = {In Memory Computing (IMC) is one of the most promising candidates for data-intensive computing accelerators of machine learning (ML). A key ML algorithm for dimensionality reduction and classification is principal component analysis (PCA), which heavily relies on matrixvector multiplications (MVM) for which classic von Neumann architectures are not optimized. Here, we provide the experimental demonstration of a new IMCbased PCA algorithm based on power iteration and deflation executed in a 4-kbit array of resistive switching random-access memory (RRAM). The classification accuracy of the Wisconsin Breast Cancer data set reaches 95.43\%, close to floatingpoint implementation. Our simulations indicate a 250× improvement in energy efficiency compared to commercial GPUs, thus supporting IMC for energy-efficient ML in modern data-intensive computing.}, language = {en} } @misc{GlukhovMiloBaronietal., author = {Glukhov, Artem and Milo, Valerio and Baroni, Andrea and Lepri, Nicola and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele}, title = {Statistical model of program/verify algorithms in resistive-switching memories for in-memory neural network accelerators}, series = {2022 IEEE International Reliability Physics Symposium (IRPS)}, journal = {2022 IEEE International Reliability Physics Symposium (IRPS)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {978-1-6654-7950-9}, issn = {2473-2001}, doi = {10.1109/IRPS48227.2022.9764497}, pages = {3C.3-1 -- 3C.3-7}, abstract = {Resistive-switching random access memory (RRAM) is a promising technology for in-memory computing (IMC) to accelerate training and inference of deep neural networks (DNNs). This work presents the first physics-based statistical model describing (i) multilevel RRAM device program/verify (PV) algorithms by controlled set transition, (ii) the stochastic cycle-to-cycle (C2C) and device-to-device (D2D) variations within the array, and (iii) the impact of such imprecisions on the accuracy of DNN accelerators. The model can handle the full chain from RRAM materials/device parameters to the DNN performance, thus providing a valuable tool for device/circuit codesign of hardware DNN accelerators.}, language = {en} } @misc{BaroniGlukhovPerezetal., author = {Baroni, Andrea and Glukhov, Artem and P{\´e}rez, Eduardo and Wenger, Christian and Calore, Enrico and Schifano, Sebastiano Fabio and Olivo, Piero and Ielmini, Daniele and Zambelli, Cristian}, title = {An energy-efficient in-memory computing architecture for survival data analysis based on resistive switching memories}, series = {Frontiers in Neuroscience}, volume = {Vol. 16}, journal = {Frontiers in Neuroscience}, issn = {1662-4548}, doi = {10.3389/fnins.2022.932270}, pages = {1 -- 16}, abstract = {One of the objectives fostered in medical science is the so-called precision medicine, which requires the analysis of a large amount of survival data from patients to deeply understand treatment options. Tools like Machine Learning and Deep Neural Networks are becoming a de-facto standard. Nowadays, computing facilities based on the Von Neumann architecture are devoted to these tasks, yet rapidly hitting a bottleneck in performance and energy efficiency. The In-Memory Computing (IMC) architecture emerged as a revolutionary approach to overcome that issue. In this work, we propose an IMC architecture based on Resistive switching memory (RRAM) crossbar arrays to provide a convenient primitive for matrix-vector multiplication in a single computational step. This opens massive performance improvement in the acceleration of a neural network that is frequently used in survival analysis of biomedical records, namely the DeepSurv. We explored how the synaptic weights mapping strategy and the programming algorithms developed to counter RRAM non-idealities expose a performance/energy trade-off. Finally, we assessed the benefits of the proposed architectures with respect to a GPU-based realization of the same task, evidencing a tenfold improvement in terms of performance and three orders of magnitude with respect to energy efficiency.}, language = {en} } @misc{BaroniGlukhovPerezetal., author = {Baroni, Andrea and Glukhov, Artem and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele and Olivo, Piero and Zambelli, Cristian}, title = {Low Conductance State Drift Characterization and Mitigation in Resistive Switching Memories (RRAM) for Artificial Neural Networks}, series = {IEEE Transactions on Device and Materials Reliability}, volume = {22}, journal = {IEEE Transactions on Device and Materials Reliability}, number = {3}, issn = {1530-4388}, doi = {10.1109/TDMR.2022.3182133}, pages = {340 -- 347}, abstract = {The crossbar structure of Resistive-switching random access memory (RRAM) arrays enabled the In-Memory Computing circuits paradigm, since they imply the native acceleration of a crucial operations in this scenario, namely the Matrix-Vector-Multiplication (MVM). However, RRAM arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation. A critical one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are mandatory for an accurate multi-level conductance operation. In this work, we analyze the benefits of a new programming algorithm that embodies Set and Reset switching operations to achieve better conductance control and lower variability. Data retention analysis performed with different temperatures for 168 hours evidence its superior performance with respect to standard programming approach. Finally, we explored the benefits of using our methodology at a higher abstraction level, through the simulation of an Artificial Neural Network for image recognition task (MNIST dataset). The accuracy achieved shows higher performance stability over temperature and time.}, language = {en} } @misc{GlukhovLepriMiloetal., author = {Glukhov, Artem and Lepri, Nicola and Milo, Valerio and Baroni, Andrea and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele}, title = {End-to-end modeling of variability-aware neural networks based on resistive-switching memory arrays}, series = {Proc. 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2022)}, journal = {Proc. 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2022)}, doi = {10.1109/VLSI-SoC54400.2022.9939653}, pages = {1 -- 5}, abstract = {Resistive-switching random access memory (RRAM) is a promising technology that enables advanced applications in the field of in-memory computing (IMC). By operating the memory array in the analogue domain, RRAM-based IMC architectures can dramatically improve the energy efficiency of deep neural networks (DNNs). However, achieving a high inference accuracy is challenged by significant variation of RRAM conductance levels, which can be compensated by (i) advanced programming techniques and (ii) variability-aware training (VAT) algorithms. In both cases, however, detailed knowledge and accurate physics-based statistical models of RRAM are needed to develop programming and VAT methodologies. This work presents an end-to-end approach to the development of highly-accurate IMC circuits with RRAM, encompassing the device modeling, the precise programming algorithm, and the VAT simulations to maximize the DNN classification accuracy in presence of conductance variations.}, language = {en} } @misc{WenBaroniPerezetal., author = {Wen, Jianan and Baroni, Andrea and P{\´e}rez, Eduardo and Ulbricht, Markus and Wenger, Christian and Krstic, Milos}, title = {Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages}, series = {2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, journal = {2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, isbn = {978-1-6654-5938-9}, issn = {2765-933X}, doi = {10.1109/DFT56152.2022.9962345}, pages = {1 -- 6}, abstract = {RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel states.}, language = {en} } @misc{PechmannPerezWengeretal., author = {Pechmann, Stefan and P{\´e}rez, Eduardo and Wenger, Christian and Hagelauer, Amelie}, title = {A current mirror Based read circuit design with multi-level capability for resistive switching deviceb}, series = {2024 International Conference on Electronics, Information, and Communication (ICEIC)}, journal = {2024 International Conference on Electronics, Information, and Communication (ICEIC)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-7188-8}, issn = {2767-7699}, doi = {10.1109/ICEIC61013.2024.10457188}, pages = {4}, abstract = {This paper presents a read circuit design for resistive memory cells based on current mirrors. The circuit utilizes high-precision current mirrors and reference cells to determine the state of resistive memory using comparators. It offers a high degree in adaptability in terms of both resistance range and number of levels. Special emphasis was put on device protection to prevent accidental programming of the memory during read operations. The realized circuit can resolve eight states with a resolution of up to 1 k Ω, realizing a digitization of the analog memory information. Furthermore, the integration in a complete memory macro is shown. The circuit was realized in a 130 nm-process but can easily be adapted to other processes and resistive memory technologies.}, language = {en} } @misc{NikiruyPerezBaronietal., author = {Nikiruy, Kristina and P{\´e}rez, Eduardo and Baroni, Andrea and Dorai Swamy Reddy, Keerthi and Pechmann, Stefan and Wenger, Christian and Ziegler, Martin}, title = {Blooming and pruning: learning from mistakes with memristive synapses}, series = {Scientific Reports}, volume = {14}, journal = {Scientific Reports}, number = {1}, issn = {2045-2322}, doi = {10.1038/s41598-024-57660-4}, abstract = {AbstractBlooming and pruning is one of the most important developmental mechanisms of the biological brain in the first years of life, enabling it to adapt its network structure to the demands of the environment. The mechanism is thought to be fundamental for the development of cognitive skills. Inspired by this, Chialvo and Bak proposed in 1999 a learning scheme that learns from mistakes by eliminating from the initial surplus of synaptic connections those that lead to an undesirable outcome. Here, this idea is implemented in a neuromorphic circuit scheme using CMOS integrated HfO2-based memristive devices. The implemented two-layer neural network learns in a self-organized manner without positive reinforcement and exploits the inherent variability of the memristive devices. This approach provides hardware, local, and energy-efficient learning. A combined experimental and simulation-based parameter study is presented to find the relevant system and device parameters leading to a compact and robust memristive neuromorphic circuit that can handle association tasks.}, language = {en} } @inproceedings{WenVargasZhuetal., author = {Wen, Jianan and Vargas, Fabian Luis and Zhu, Fukun and Reiser, Daniel and Baroni, Andrea and Fritscher, Markus and P{\´e}rez, Eduardo and Reichenbach, Marc and Wenger, Christian and Krstic, Milos}, title = {Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment}, series = {2024 IEEE 25th Latin American Test Symposium (LATS)}, booktitle = {2024 IEEE 25th Latin American Test Symposium (LATS)}, publisher = {IEEE}, doi = {10.1109/LATS62223.2024.10534601}, pages = {6}, abstract = {Emerging device technologies such as resistive RAM (RRAM) are increasingly recognized in enhancing system performance, particularly in applications demanding extensive vector-matrix multiplications (VMMs) with high parallelism. However, a significant limitation in current electronics design automation (EDA) tools is their lack of support for rapid prototyping, design space exploration, and the integration of inherent process-dependent device variability into system-level simulations, which is essential for assessing system reliability. To address this gap, we introduce a field-programmable gate array (FPGA) based emulation approach for RRAM crossbars featuring cycle-accurate emulations in real time without relying on complex device models. Our approach is based on pre-generated look-up tables (LUTs) to accurately represent the RRAM device behavior. To efficiently model the device variability at the system level, we propose using the multivariate kernel density estimation (KDE) method to augment the measured RRAM data. The proposed emulator allows precise latency determination for matrix mapping and computation operations. Meanwhile, by coupling with the NeuroSim framework, the corresponding energy consumption can be estimated. In addition to facilitating a range of in-depth system assessments, experimental results suggest a remarkable reduction of emulation time compared to the classic behavioral simulation.}, language = {en} } @misc{DoraiSwamyReddyPerezBaronietal., author = {Dorai Swamy Reddy, Keerthi and P{\´e}rez, Eduardo and Baroni, Andrea and Mahadevaiah, Mamathamba Kalishettyhalli and Marschmeyer, Steffen and Fraschke, Mirko and Lisker, Marco and Wenger, Christian and Mai, Andreas}, title = {Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance}, series = {The European Physical Journal B}, volume = {97}, journal = {The European Physical Journal B}, publisher = {Springer Science and Business Media LLC}, issn = {1434-6028}, doi = {10.1140/epjb/s10051-024-00821-1}, pages = {9}, abstract = {Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal-insulator-metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2 dielectric thickness from 8 nm to 5 nm. Additionally, 5\% Al-doped 4 nm HfO2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology.}, language = {en} } @misc{MaldonadoCantudoSwamyReddyetal., author = {Maldonado, David and Cantudo, Antonio and Swamy Reddy, Keerthi Dorai and Pechmann, Stefan and Uhlmann, Max and Wenger, Christian and Roldan, Juan Bautista and P{\´e}rez, Eduardo}, title = {Influence of stop and gate voltage on resistive switching of 1T1R HfO2-based memristors, a modeling and variability analysis}, series = {Materials Science in Semiconductor Processing}, volume = {182}, journal = {Materials Science in Semiconductor Processing}, issn = {1873-4081}, doi = {10.1016/j.mssp.2024.108726}, pages = {9}, language = {en} } @misc{VinuesaGarciaPerezetal., author = {Vinuesa, Guillermo and Garc{\´i}a, H{\´e}ctor and P{\´e}rez, Eduardo and Wenger, Christian and {\´I}{\~n}iguez de la Torre, Ignacio and Gonz{\´a}lez, Tom{\´a}s and Due{\~n}as, Salvador and Cast{\´a}n, Helena}, title = {On the asymmetry of Resistive Switching Transitions}, series = {Electronics}, volume = {13}, journal = {Electronics}, number = {13}, publisher = {MDPI}, issn = {2079-9292}, doi = {10.3390/electronics13132639}, pages = {11}, abstract = {In this study, the resistive switching phenomena in TiN/Ti/HfO2/Ti metal-insulator-metal stacks is investigated, mainly focusing on the analysis of set and reset transitions. The electrical measurements in a wide temperature range reveal that the switching transitions require less voltage (and thus, less energy) as temperature rises, with the reset process being much more temperature sensitive. The main conduction mechanism in both resistance states is Space-charge-limited Conduction, but the high conductivity state also shows Schottky emission, explaining its temperature dependence. Moreover, the temporal evolution of these transitions reveals clear differences between them, as their current transient response is completely different. While the set is sudden, the reset process development is clearly non-linear, closely resembling a sigmoid function. This asymmetry between switching processes is of extreme importance in the manipulation and control of the multi-level characteristics and has clear implications in the possible applications of resistive switching devices in neuromorphic computing.}, language = {en} } @misc{VinuesaGarciaDuenasetal., author = {Vinuesa, Guillermo and Garcia, Hector and Duenas, Salvador and Castan, Helena and I{\~n}iguez de la Torre, Ignacio and Gonzalez, Tomas and Dorai Swamy Reddy, Keerthi and Uhlmann, Max and Wenger, Christian and Perez, Eduardo}, title = {Effect of the temperature on the performance and dynamic behavior of HfO2-Based Rram Devices}, series = {ECS Meeting Abstracts}, volume = {MA2024-01}, journal = {ECS Meeting Abstracts}, number = {21}, publisher = {The Electrochemical Society}, issn = {2151-2043}, doi = {10.1149/MA2024-01211297mtgabs}, pages = {1297 -- 1297}, abstract = {Over the past decades, the demand for semiconductor memory devices has been steadily increasing, and is currently experiencing an unprecedented boost due to the development and expansion of artificial intelligence. Among emerging high-density non-volatile memories, resistive random-access memory (RRAM) is one of the best recourses for all kind of applications, such as neuromorphic computing or hardware security [1]. Although many materials have been evaluated for RRAM development, some of them with excellent results, HfO2 is one of the established materials in CMOS domain due to its compatibility with standard materials and processes [2]. The main goal of this work is to study the switching capability and stability of HfO2-based RRAMs, as well as to explore their ability in the field of analogue applications, by analyzing the evolution of the resistance states that allow multilevel control. Indeed, analogue operation is a key point for achieving electronic neural synapses in neuromorphic systems, with synaptic weight information encoded in the different resistance states. This research has been carried out over a wide temperature range, between 40 and 340 K, as we are interested in testing the extent to which performance is maintained or modified, with a view to designing neuromorphic circuits that are also suitable in the low-temperature realm. We aim to prove that these simple, fast, high integration density structures can also be used in circuits designed for specific applications, such as aerospace systems. The RRAM devices studied in this work are TiN/Ti/8 nm-HfO2/TiN metal-insulator-metal (MIM) capacitors. Dielectric layers were atomic layer deposited (ALD). It has been demonstrated that the Ti coat in the top electrode acts as a scavenger that absorbs oxygen atoms from the HfO2 layer, and facilitates the creation of conductive filaments of oxygen vacancies [3]. In fact, the oxygen reservoir capability of Ti is well known, as it is able to attract and release oxygen atoms from or to the HfO2 layer during the RRAM operation [4]. The clustering of vacancies extends through the entire thickness of the oxide and, after an electroformig step, it joins the upper and lower electrodes and the device reaches the low resistance state (LRS). By applying adequate electrical signals, the filaments can be partially dissolved, which brings the device into the high-resistance state (HRS), with lower current values. The set process brings the device to the LRS state, while the reset one brings it to the HRS. The dependence of electrical conductivity on external applied electrical excitation allows triggering the device between the both states in a non-volatile manner [5]. The experimental equipment used consisted of a Keithley 4200-SCS semiconductor parameter analyzer and a Lake Shore cryogenic probe station. Fig.1 shows current-voltage cycles measured at different temperatures; the averages values at each temperature, both in logarithmic and linear scale, are also shown. The functional window increases as temperature decreases. The evolutions of set and reset voltage values with temperature are depicted in Fig.2, whereas the current values (measured at 0.1 V) corresponding to the LRS and HRS can be seen in Fig.3. LRS resistance decreases as temperature increases, in agreement with semiconductor behaviour, probably due to a hopping conduction mechanism. Both set and reset voltages decrease as temperature increases; the reset process is smoother at high temperatures. The reduction in reset voltage variability as temperature increases is very notable. Finally, Fig. 4 shows a picture of the transient behaviour; in the right panel of the same figure, the amplitudes of the current transients in the reset state have been included in the external loop. To sum up, the resistive switching phenomena is studied in a wide temperature range. The LRS shows semiconducting behavior with temperature, most likely related to a hopping conduction mechanism. Switching voltages decrease as temperature increases, with a notable reduction in reset voltage variability. An excellent control of intermediate resistance state is shown through current transients at several voltages in the reset process. REFERENCES [1] M. Asif et al., Materials Today Electronics 1, 100004 (2022). [2] S. Slesazeck et al., Nanotechnology 30, 352003 (2019). [3] Z. Fang et al., IEEE Electron Device Letters 35, 9, 912-914 (2014). [4] H. Y. Lee et al., IEEE Electron Device Letters 31, 1, 44-46 (2010). [5] D. J. Wouters et al., Proceedings of the IEEE 103, 8, 1274-1288 (2015). Figure 1}, language = {en} } @misc{DerschRoemerPerezetal., author = {Dersch, Nadine and Roemer, Christian and Perez, Eduardo and Wenger, Christian and Schwarz, Mike and I{\~n}{\´i}guez, Benjam{\´i}n and Kloes, Alexander}, title = {Fast circuit simulation of memristive crossbar arrays with bimodal stochastic synaptic weights}, series = {2024 IEEE Latin American Electron Devices Conference (LAEDC)}, journal = {2024 IEEE Latin American Electron Devices Conference (LAEDC)}, publisher = {IEEE}, isbn = {979-8-3503-6130-8}, issn = {979-8-3503-6129-2}, doi = {10.1109/LAEDC61552.2024.10555829}, pages = {1 -- 4}, abstract = {This paper presents an approach for highly efficient circuit simulation of hardware-based artificial neural networks by using memristive crossbar array architectures. There are already possibilities to test neural networks with stochastic weights via simulations like the macro model NeuroSim. However, the noise-based variability approach offers more realistic setting options including elements of a classical circuit simulation for more precise analysis of neural networks. With this approach, statistical parameter fluctuations can be simulated based on different distribution functions of devices. In Cadence Virtuoso, a simulation of a crossbar array with 10 synaptic weights following a bimodal distribution, the new approach shows a 1,000x speedup compared to a Monte Carlo simulation. Initial tests of a memristive crossbar array with over 15,000 stochastic weights to classify the MNIST dataset show that the new approach can be used to test the functionality of hardware-based neural networks.}, language = {en} } @misc{WenBaroniPerezetal., author = {Wen, Jianan and Baroni, Andrea and Perez, Eduardo and Uhlmann, Max and Fritscher, Markus and KrishneGowda, Karthik and Ulbricht, Markus and Wenger, Christian and Krstic, Milos}, title = {Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator}, series = {2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}, journal = {2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}, publisher = {IEEE}, isbn = {978-3-9819263-8-5}, issn = {1558-1101}, doi = {10.23919/DATE58400.2024.10546709}, pages = {1 -- 6}, abstract = {The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 \% and 18 \%, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83\% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero.}, language = {en} } @misc{MaldonadoBaroniAldanaetal., author = {Maldonado, David and Baroni, Andrea and Aldana, Samuel and Dorai Swamy Reddy, Keerthi and Pechmann, Stefan and Wenger, Christian and Rold{\´a}n, Juan Bautista and P{\´e}rez, Eduardo}, title = {Kinetic Monte Carlo simulation analysis of the conductance drift in Multilevel HfO2-based RRAM devices}, series = {Nanoscale}, volume = {16}, journal = {Nanoscale}, number = {40}, publisher = {Royal Society of Chemistry (RSC)}, issn = {2040-3364}, doi = {10.1039/d4nr02975e}, pages = {19021 -- 19033}, abstract = {The drift characteristics of valence change memory (VCM) devices have been analyzed through both experimental analysis and 3D kinetic Monte Carlo (kMC) simulations.}, language = {en} } @misc{PetrykDykaPerezetal., author = {Petryk, Dmytro and Dyka, Zoya and P{\´e}rez, Eduardo and Kabin, Ievgen and Katzer, Jens and Sch{\"a}ffner, Jan and Langend{\"o}rfer, Peter}, title = {Sensitivity of HfO2-based RRAM Cells to Laser Irradiation}, series = {Microprocessors and Microsystems}, journal = {Microprocessors and Microsystems}, number = {87}, issn = {0141-9331}, doi = {10.1016/j.micpro.2021.104376}, language = {en} } @misc{WenVargasZhuetal., author = {Wen, Jianan and Vargas, Fabian Luis and Zhu, Fukun and Reiser, Daniel and Baroni, Andrea and Fritscher, Markus and Perez, Eduardo and Reichenbach, Marc and Wenger, Christian and Krstic, Milos}, title = {RRAMulator : an efficient FPGA-based emulator for RRAM crossbar with device variability and energy consumption evaluation}, series = {Microelectronics Reliability}, volume = {168}, journal = {Microelectronics Reliability}, publisher = {Elsevier BV}, address = {Amsterdam}, issn = {0026-2714}, doi = {10.1016/j.microrel.2025.115630}, pages = {1 -- 10}, abstract = {The in-memory computing (IMC) systems based on emerging technologies have gained significant attention due to their potential to enhance performance and energy efficiency by minimizing data movement between memory and processing unit, which is especially beneficial for data-intensive applications. Designing and evaluating systems utilizing emerging memory technologies, such as resistive RAM (RRAM), poses considerable challenges due to the limited support from electronics design automation (EDA) tools for rapid development and design space exploration. Additionally, incorporating technology-dependent variability into system-level simulations is critical to accurately assess the impact on system reliability and performance. To bridge this gap, we propose RRAMulator, a field-programmable gate array (FPGA) based hardware emulator for RRAM crossbar array. To avoid the complex device models capturing the nonlinear current-voltage (IV) relationships that degrade emulation speed and increase hardware utilization, we propose a device and variability modeling approach based on device measurements. We deploy look-up tables (LUTs) for device modeling and use the multivariate kernel density estimation (KDE) method to augment existing data, extending data variety and avoiding repetitive data usage. The proposed emulator achieves cycle-accurate, real-time emulations and provides information such as latency and energy consumption for matrix mapping and vector-matrix multiplications (VMMs). Experimental results show a significant reduction in emulation time compared to conventional behavioral simulations. Additionally, an RRAM-based discrete Fourier transform (DFT) accelerator is analyzed as a case study featuring a range of in-depth system assessments.}, language = {en} } @misc{UhlmannKrysikWenetal., author = {Uhlmann, Max and Krysik, Milosz and Wen, Jianan and Frohberg, Max and Baroni, Andrea and Reddy, Keerthi Dorai Swamy and P{\´e}rez, Eduardo and Ostrovskyy, Philip and Piotrowski, Krzysztof and Carta, Corrado and Wenger, Christian and Kahmen, Gerhard}, title = {A compact one-transistor-multiple-RRAM characterization platform}, series = {IEEE transactions on circuits and systems I : regular papers}, journal = {IEEE transactions on circuits and systems I : regular papers}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {1549-8328}, doi = {10.1109/TCSI.2025.3555234}, pages = {1 -- 12}, abstract = {Emerging non-volatile memories (eNVMs) such as resistive random-access memory (RRAM) offer an alternative solution compared to standard CMOS technologies for implementation of in-memory computing (IMC) units used in artificial neural network (ANN) applications. Existing measurement equipment for device characterisation and programming of such eNVMs are usually bulky and expensive. In this work, we present a compact size characterization platform for RRAM devices, including a custom programming unit IC that occupies less than 1 mm2 of silicon area. Our platform is capable of testing one-transistor-one-RRAM (1T1R) as well as one-transistor-multiple-RRAM (1TNR) cells. Thus, to the best knowledge of the authors, this is the first demonstration of an integrated programming interface for 1TNR cells. The 1T2R IMC cells were fabricated in the IHP's 130 nm BiCMOS technology and, in combination with other parts of the platform, are able to provide more synaptic weight resolution for ANN model applications while simultaneously decreasing the energy consumption by 50 \%. The platform can generate programming voltage pulses with a 3.3 mV accuracy. Using the incremental step pulse with verify algorithm (ISPVA) we achieve 5 non-overlapping resistive states per 1T1R device. Based on those 1T1R base states we measure 15 resulting state combinations in the 1T2R cells.}, language = {en} } @misc{BaroniPerezReddyetal., author = {Baroni, Andrea and P{\´e}rez, Eduardo and Reddy, Keerthi Dorai Swamy and Pechmann, Stefan and Wenger, Christian and Ielmini, Daniele and Zambelli, Cristian}, title = {Enhancing RRAM reliability : exploring the effects of Al doping on HfO2-based devices}, series = {IEEE transactions on device and materials reliability}, journal = {IEEE transactions on device and materials reliability}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {1530-4388}, doi = {10.1109/TDMR.2025.3581061}, pages = {1 -- 9}, abstract = {This study provides a comprehensive evaluation of RRAM devices based on HfO2 and Al-doped HfO2 insulators, focusing on critical performance metrics, including Forming yield, Post-Programming Stability (PPS), Fast Drift, Endurance, and Retention at elevated temperatures (125 ∘C). Aluminum doping significantly enhances device reliability and stability, improving Forming yield, reducing current drift during programming and Retention tests, and minimizing variability during Endurance cycling. While Al5\%:HfO2 achieves most of the observed benefits compared to pure HfO2, Al7\%:HfO2 offers incremental advantages for scenarios requiring extreme reliability. These findings position Al-doped HfO2 devices as a promising solution for RRAM-based systems in memory and neuromorphic computing, highlighting the potential trade-off between performance gains and increased fabrication complexity. This work underlines the importance of material engineering for optimizing RRAM devices in application-specific contexts.}, language = {en} } @misc{BlumensteinPerezWengeretal., author = {Blumenstein, Alan and P{\´e}rez, Eduardo and Wenger, Christian and Dersch, Nadine and Kloes, Alexander and I{\~n}{\´i}guez, Benjam{\´i}n and Schwarz, Mike}, title = {Evaluating device variability in RRAM-based single- and multi-layer perceptrons}, series = {2025 32nd International Conference on Mixed Design of Integrated Circuits and System (MIXDES)}, journal = {2025 32nd International Conference on Mixed Design of Integrated Circuits and System (MIXDES)}, publisher = {IEEE}, address = {New York}, isbn = {978-83-63578-27-5}, doi = {10.23919/MIXDES66264.2025.11092102}, pages = {74 -- 77}, abstract = {This work investigates the impact of stochastic weight variations in hardware implementations of artificial neural networks, focusing on a Single-Layer Perceptron and Multi-Layer Perceptrons. A variable neural network model is introduced, applying Gaussian variability to synaptic weights based on an adjustment rate, which controls the proportion of affected weights. By studying how stochastic variations affect accuracy, simulations under device-to-device and cycle-to-cycle variation conditions demonstrate that Single-Layer Perceptrons are more sensitive to weight variations, while Multi-Layer perceptrons show greater robustness. Additionally, stochastic quantization improves the performance of Multi-Layer Perceptrons but has minimal effect on Single-Layer Perceptrons.}, language = {en} } @misc{WenBaroniUhlmannetal., author = {Wen, Jianan and Baroni, Andrea and Uhlmann, Max and Perez, Eduardo and Wenger, Christian and Krstic, Milos}, title = {ReFFT : an energy-efficient RRAM-based FFT accelerator}, series = {IEEE transactions on computer-aided design of integrated circuits and systems}, journal = {IEEE transactions on computer-aided design of integrated circuits and systems}, publisher = {IEEE}, address = {Piscataway, NJ}, issn = {0278-0070}, doi = {10.1109/TCAD.2025.3627146}, pages = {1 -- 14}, abstract = {The fast Fourier transform (FFT) is a highly efficient algorithm for computing the discrete Fourier transform (DFT). It is widely employed in various applications, including digital communication, image processing, and signal analysis. Recently, in-memory computing architectures based on emerging technologies, such as resistive RAM (RRAM), have demonstrated promising performance with low hardware cost for data-intensive applications. However, directly mapping FFT onto RRAM crossbars is challenging because the algorithm relies on many small, sequential butterfly operations, while cross-bars are optimized for large-scale, highly parallel vector-matrix multiplications (VMMs). In this paper, we introduce ReFFT, a system architecture that reformulates FFT computations for efficient execution on RRAM crossbars. ReFFT combines the reduced computational complexity of FFT with the parallel VMM capability of RRAM. We incorporate measured device data into our framework to analyze the effect of variability and develop an adaptive mapping scheme that improves twiddle-factor programming accuracy, leading to a 9.9 dB peak signal-to-noise ratio (PSNR) improvement for a 256-point FFT. Compared with prior RRAM-based DFT designs, ReFFT achieves up to 4.6× and 19.5× higher energy efficiency for 256- and 2048-point FFTs, respectively. The system is further validated in digital communication and satellite image compression tasks.}, language = {en} } @misc{DerschPerezWengeretal., author = {Dersch, Nadine and Perez, Eduardo and Wenger, Christian and Lanza, Mario and Zhu, Kaichen and Schwarz, Mike and I{\~n}{\´i}guez, Benjam{\´i}n and Kloes, Alexander}, title = {Statistical model for the calculation of conductance variations of memristive devices}, series = {2025 IEEE European Solid-State Electronics Research Conference (ESSERC)}, journal = {2025 IEEE European Solid-State Electronics Research Conference (ESSERC)}, publisher = {IEEE}, address = {Piscataway, NJ}, doi = {10.1109/ESSERC66193.2025.11213973}, pages = {373 -- 376}, abstract = {This paper presents a statistical model which calculates the expected conductance variations from device to device or from cycle to cycle of memristive devices. The mean readout current and its standard deviation can be calculated for binary and multi-level devices. These values are important for simulating hardware-based artificial neural networks at circuit level and testing their functionality. Research into hardwarebased artificial neural networks is important because they are energy-efficient. Furthermore to calculating the variations, the statistical model can be used to determine what influence the cumulative distribution function of switching has on the variations and which behavior provides the best results for the hardwarebased artificial neural network. Some memristive devices exhibit multi-level behavior due to defects in the switching layer. The number of these defects and the optimal amount can be estimated.}, language = {en} } @misc{DerschPerezWengeretal., author = {Dersch, Nadine and Perez, Eduardo and Wenger, Christian and Schwarz, Mike and Iniguez, Benjamin and Kloes, Alexander}, title = {A closed-form model for programming of oxide-based resistive random access memory cells derived from the Stanford model}, series = {Solid-state electronics}, volume = {230}, journal = {Solid-state electronics}, publisher = {Elsevier BV}, address = {Amsterdam}, issn = {0038-1101}, doi = {10.1016/j.sse.2025.109238}, pages = {1 -- 5}, abstract = {This paper presents a closed-form model for pulse-based programming of oxide-based resistive random access memory devices. The Stanford model is used as a basis and solved in a closed-form for the programming cycle. A constant temperature is set for this solution. With the closed-form model, the state of the device after programming or the required programming settings for achieving a specific device conductance can be calculated directly and quickly. The Stanford model requires time-consuming iterative calculations for high accuracy in transient analysis, which is not necessary for the closed-form model. The closed-form model is scalable across different programming pulse widths and voltages.}, language = {en} } @misc{WenBaroniMistronietal., author = {Wen, Jianan and Baroni, Andrea and Mistroni, Alberto and Perez, Eduardo and Zambelli, Cristian and Wenger, Christian and Krstic, Milos and Bolzani P{\"o}hls, Leticia Maria}, title = {ReDiM : an efficient strategy for read disturb mitigation in RRAM-based accelerators}, series = {2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS)}, journal = {2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS)}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {979-8-3315-3334-2}, doi = {10.1109/IOLTS65288.2025.11117065}, pages = {1 -- 7}, abstract = {Resistive RAM (RRAM) has emerged as a promising non-volatile memory technology for implementing energy-efficient hardware accelerators within the in-memory computing (IMC) paradigm. However, due to the immature fabrication process and inherent material instabilities, frequent read operations during computations can induce read disturb effects, leading to unintended resistance drift and potential data corruption. Existing mitigation approaches primarily focus on detecting read disturb effects and triggering memory refresh operations. In this work, we propose an architecture-level solution that mitigates read disturb in RRAM-based accelerators. Our strategy employs crossbar duplication and decomposes the single high input pulse into two lower-amplitude pulses, effectively minimizing the risk of read disturb. To validate our approach, we develop a simulation framework that incorporates measurement data from characterized RRAM devices under read disturb stress conditions. Experimental results on VGG-8 with CIFAR-10 demonstrate that the proposed method significantly mitigates inference accuracy degradation caused by read disturb in RRAM-based accelerators, while incurring modest area and energy overheads of 12.32\% and 2.15\%, respectively. This work provides a practical and scalable solution for enhancing the robustness of RRAM-based accelerators in edge and high-performance computing applications.}, language = {en} } @misc{BlumensteinPerezWengeretal., author = {Blumenstein, Alan and P{\´e}rez, Eduardo and Wenger, Christian and Dersch, Nadine and Kloes, Alexander and I{\~n}{\´i}guez, Benjam{\´i}n and Schwarz, Mike}, title = {Exploring variability and quantization effects in artificial neural networks using the MNIST dataset}, series = {Solid-state electronics}, volume = {232}, journal = {Solid-state electronics}, publisher = {Elsevier BV}, address = {Amsterdam}, issn = {0038-1101}, doi = {10.1016/j.sse.2025.109296}, pages = {1 -- 4}, abstract = {This paper investigates the impact of introducing variability to trained neural networks and examines the effects of variability and quantization on network accuracy. The study utilizes the MNIST dataset to evaluate various Multi-Layer Perceptron configurations: a baseline model with a Single-Layer Perceptron and an extended model with multiple hidden nodes. The effects of Cycle-to-Cycle variability on network accuracy are explored by varying parameters such as the standard deviation to simulate dynamic changes in network weights. In particular, the performance differences between the Single-Layer Perceptron and the Multi-Layer Perceptron with hidden layers are analyzed, highlighting the network's robustness to stochastic perturbations. These results provide insights into the effects of quantization and network architecture on accuracy under varying levels of variability.}, language = {en} } @misc{PerezMaldonadoPechmannetal., author = {Perez, Eduardo and Maldonado, David and Pechmann, Stefan and Reddy, Keerthi Dorai Swamy and Uhlmann, Max and Hagelauer, Amelie and Roldan, Juan Bautista and Wenger, Christian}, title = {Impact of the series resistance on switching characteristics of 1T1R HfO₂-based RRAM devices}, series = {2025 15th Spanish Conference on Electron Devices (CDE)}, journal = {2025 15th Spanish Conference on Electron Devices (CDE)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {Piscataway, NJ}, isbn = {979-8-3315-9618-7}, doi = {10.1109/CDE66381.2025.11038868}, pages = {1 -- 4}, abstract = {This study investigates the influence of the series resistance (RS) on the switching characteristics of 1-transistor-1-resistor (1T1R) RRAM devices based on HfO2 and Al:HfO₂ dielectrics. Intrinsic RS values were extracted from I-V characteristics measured over 50 Reset-Set cycles at various gate voltages (VG) by using a numerical transformation method. Results reveal the contribution of the transistor's resistance to the overall RS. A linear relationship between RS values and Set transition voltages (VTS) was found, with larger RS values amplifying the variability in switching parameters. Comparative analysis of cumulative distribution functions (CDFs) highlights differences between technologies, showing lower VTS values as well as lower sensitivity to RS for Al:HfO₂-based devices. These findings underscore the critical role of RS in modeling and optimizing the performance of RRAM devices for reliable operation.}, language = {en} }