@misc{PerezAvilaGonzalezCorderoPerezetal., author = {Perez-Avila, Antonio Javier and Gonzalez-Cordero, Gerardo and P{\´e}rez, Eduardo and Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Wenger, Christian and Roldan, Juan Bautista and Jimenez-Molinos, Francisco}, title = {Behavioral modeling of multilevel HfO2-based memristors for neuromorphic circuit simulation}, series = {XXXV Conference on Design of Circuits and Integrated Systems (DCIS), Segovia, Spain}, journal = {XXXV Conference on Design of Circuits and Integrated Systems (DCIS), Segovia, Spain}, doi = {10.1109/DCIS51330.2020.9268652}, abstract = {An artificial neural network based on resistive switching memristors is implemented and simulated in LTspice. The influence of memristor variability and the reduction of the continuous range of synaptic weights into a discrete set of conductance levels is analyzed. To do so, a behavioral model is proposed for multilevel resistive switching memristors based on Al-doped HfO2 dielectrics, and it is implemented in a spice based circuit simulator. The model provides an accurate description of the conductance in the different conductive states in addition to describe the device-to-device variability}, language = {en} } @misc{PerezPerezAvilaRomeroZalizetal., author = {P{\´e}rez, Eduardo and P{\´e}rez-{\´A}vila, Antonio Javier and Romero-Zaliz, Roc{\´i}o and Mahadevaiah, Mamathamba Kalishettyhalli and P{\´e}rez-Bosch Quesada, Emilio and Roldan, Juan Bautista and Jim{\´e}nez-Molinos, Francisco and Wenger, Christian}, title = {Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing}, series = {Electronics (MDPI)}, volume = {10}, journal = {Electronics (MDPI)}, number = {9}, issn = {2079-9292}, doi = {10.3390/electronics10091084}, pages = {15}, abstract = {Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8×8 vector-matrixmultiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6\% compared with the use of non-optimized parameters.}, language = {en} } @misc{PerezBoschQuesadaRomeroZalizPerezetal., author = {P{\´e}rez-Bosch Quesada, Emilio and Romero-Zaliz, Roc{\´i}o and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Reuben, John and Schubert, Markus Andreas and Jim{\´e}nez-Molinos, Francisco and Rold{\´a}n, Juan Bautista and Wenger, Christian}, title = {Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems}, series = {Electronics (MDPI)}, volume = {10}, journal = {Electronics (MDPI)}, number = {6}, issn = {2079-9292}, doi = {10.3390/electronics10060645}, pages = {13}, abstract = {In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.}, language = {en} } @misc{PechmannMaiVoelkeletal., author = {Pechmann, Stefan and Mai, Timo and V{\"o}lkel, Matthias and Mahadevaiah, Mamathamba Kalishettyhalli and P{\´e}rez, Eduardo and Perez-Bosch Quesada, Emilio and Reichenbach, Marc and Wenger, Christian and Hagelauer, Amelie}, title = {A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells}, series = {Electronics}, volume = {10}, journal = {Electronics}, number = {5}, issn = {2079-9292}, doi = {10.3390/electronics10050530}, pages = {17}, abstract = {In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.}, language = {en} } @misc{PerezMahadevaiahPerezBoschQuesadaetal., author = {P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Perez-Bosch Quesada, Emilio and Wenger, Christian}, title = {Variability and Energy Consumption Tradeoffs in Multilevel Programming of RRAM Arrays}, series = {IEEE Transactions on Electron Devices}, volume = {68}, journal = {IEEE Transactions on Electron Devices}, number = {6}, issn = {0018-9383}, doi = {10.1109/TED.2021.3072868}, pages = {2693 -- 2698}, abstract = {Achieving a reliable multi-level programming operation in resistive random access memory (RRAM) arrays is still a challenging task. In this work, we assessed the impact of the voltage step value used by the programming algorithm on the device-to-device (DTD) variability of the current distributions of four conductive levels and on the energy consumption featured by programming 4-kbit HfO2-based RRAM arrays. Two different write-verify algorithms were considered and compared, namely, the incremental gate voltage with verify algorithm (IGVVA) and the incremental step pulse with verify algorithm (ISPVA). By using the IGVVA, a main trade-off has to be taken into account since reducing the voltage step leads to a smaller DTD variability at the cost of a strong increase in the energy consumption. Although the ISPVA can not reduce the DTD variability as much as the IGVVA, its voltage step can be decreased in order to reduce the energy consumption with almost no impact on the DTD variability. Therefore, the final decision on which algorithm to employ should be based on the specific application targeted for the RRAM array.}, language = {en} } @misc{PerezBoschQuesadaPerezMahadevaiahetal., author = {Perez-Bosch Quesada, Emilio and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Wenger, Christian}, title = {Memristive-based in-memory computing: from device to large-scale CMOS integration}, series = {Neuromorphic Computing and Engineering}, volume = {1}, journal = {Neuromorphic Computing and Engineering}, number = {2}, issn = {2634-4386}, doi = {10.1088/2634-4386/ac2cd4}, pages = {8}, abstract = {With the rapid emergence of in-memory computing systems based on memristive technology, the integration of such memory devices in large-scale architectures is one of the main aspects to tackle. In this work we present a study of HfO2-based memristive devices for their integration in large-scale CMOS systems, namely 200 mm wafers. The DC characteristics of single metal-insulator-metal devices are analyzed taking under consideration device-to-device variabilities and switching properties. Furthermore, the distribution of the leakage current levels in the pristine state of the samples are analyzed and correlated to the amount of formingless memristors found among the measured devices. Finally, the obtained results are fitted into a physic-based compact model that enables their integration into larger-scale simulation environments.}, language = {en} } @misc{BischoffLeisePerezBoschQuesadaetal., author = {Bischoff, Carl and Leise, Jakob and Perez-Bosch Quesada, Emilio and P{\´e}rez, Eduardo and Wenger, Christian and Kloes, Alexander}, title = {Implementation of device-to-device and cycle-to-cycle variability of memristive devices in circuit simulations}, series = {Solid-State Electronics}, volume = {194}, journal = {Solid-State Electronics}, issn = {0038-1101}, doi = {10.1016/j.sse.2022.108321}, pages = {4}, abstract = {We present a statistical procedure for the extraction of parameters of a compact model for memristive devices. Thereby, in a circuit simulation the typical fluctuations of the current-voltage (I-V) characteristics from device-to-device (D2D) and from cycle-to-cycle (C2C) can be emulated. The approach is based on the Stanford model whose parameters play a key role to integrating D2D and C2C dispersion. The influence of such variabilities over the model's parameters is investigated by using a fitting algorithm fed with experimental data. After this, the statistical distributions of the parameters are used in a Monte Carlo simulation to reproduce the I-V D2D and C2C dispersions which show a good agreement to the measured curves. The results allow the simulation of the on/off current variation for the design of RRAM cells or memristor-based artificial neural networks.}, language = {en} } @misc{MahadevaiahPerezLiskeretal., author = {Mahadevaiah, Mamathamba Kalishettyhalli and P{\´e}rez, Eduardo and Lisker, Marco and Schubert, Markus Andreas and Perez-Bosch Quesada, Emilio and Wenger, Christian and Mai, Andreas}, title = {Modulating the Filamentary-Based Resistive Switching Properties of HfO2 Memristive Devices by Adding Al2O3 Layers}, series = {Electronics : open access journal}, volume = {11}, journal = {Electronics : open access journal}, number = {10}, issn = {2079-9292}, doi = {10.3390/electronics11101540}, pages = {14}, abstract = {The resistive switching properties of HfO2 based 1T-1R memristive devices are electrically modified by adding ultra-thin layers of Al2O3 into the memristive device. Three different types of memristive stacks are fabricated in the 130 nm CMOS technology of IHP. The switching properties of the memristive devices are discussed with respect to forming voltages, low resistance state and high resistance state characteristics and their variabilities. The experimental I-V characteristics of set and reset operations are evaluated by using the quantum point contact model. The properties of the conduction filament in the on and off states of the memristive devices are discussed with respect to the model parameters obtained from the QPC fit.}, language = {en} } @misc{PerezMahadevaiahPerezBoschQuesadaetal., author = {P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Perez-Bosch Quesada, Emilio and Wenger, Christian}, title = {In-depth characterization of switching dynamics in amorphous HfO2 memristive arrays for the implementation of synaptic updating rules}, series = {Japanese Journal of Applied Physics}, volume = {61}, journal = {Japanese Journal of Applied Physics}, issn = {0021-4922}, doi = {10.35848/1347-4065/ac6a3b}, pages = {1 -- 7}, abstract = {Accomplishing truly analog conductance modulation in memristive arrays is crucial in order to implement the synaptic plasticity in hardware-based neuromorphic systems. In this paper, such a feature was addressed by exploiting the inherent stochasticity of switching dynamics in amorphous HfO2 technology. A thorough statistical analysis of experimental characteristics measured in 4 kbit arrays by using trains of identical depression/potentiation pulses with different voltage amplitudes and pulse widths provided the key to develop two different updating rules and to define their optimal programming parameters. The first rule is based on applying a specific number of identical pulses until the conductance value achieves the desired level. The second one utilized only one single pulse with a particular amplitude to achieve the targeted conductance level. In addition, all the results provided by the statistical analysis performed may play an important role in understanding better the switching behavior of this particular technology.}, language = {en} } @misc{BogunPerezBoschQuesadaPerezetal., author = {Bogun, Nicolas and Perez-Bosch Quesada, Emilio and P{\´e}rez, Eduardo and Wenger, Christian and Kloes, Alexander and Schwarz, Mike}, title = {Analytical Calculation of Inference in Memristor-based Stochastic Artificial Neural Networks}, series = {29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES), 23-24 June 2022 , Wrocław, Poland}, journal = {29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES), 23-24 June 2022 , Wrocław, Poland}, isbn = {978-83-63578-22-0}, doi = {10.23919/MIXDES55591.2022.9838321}, pages = {83 -- 88}, abstract = {The impact of artificial intelligence on human life has increased significantly in recent years. However, as the complexity of problems rose aswell, increasing system features for such amount of data computation became troublesome due to the von Neumann's computer architecture. Neuromorphic computing aims to solve this problem by mimicking the parallel computation of a human brain. For this approach, memristive devices are used to emulate the synapses of a human brain. Yet, common simulations of hardware based networks require time consuming Monte-Carlo simulations to take into account the stochastic switching of memristive devices. This work presents an alternative concept making use of the convolution of the probability distribution functions (PDF) of memristor currents by its equivalent multiplication in Fourier domain. An artificial neural network is accordingly implemented to perform the inference stage with handwritten digits.}, language = {en} } @misc{PerezMaldonadoPerezBoschQuesadaetal., author = {P{\´e}rez, Eduardo and Maldonado, David and Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Jimenez-Molinos, Francisco and Wenger, Christian}, title = {Parameter Extraction Methods for Assessing Device-to-Device and Cycle-to-Cycle Variability of Memristive Devices at Wafer Scale}, series = {IEEE Transactions on Electron Devices}, volume = {70}, journal = {IEEE Transactions on Electron Devices}, number = {1}, issn = {0018-9383}, doi = {10.1109/TED.2022.3224886}, pages = {360 -- 365}, abstract = {The stochastic nature of the resistive switching (RS) process in memristive devices makes device-to-device (DTD) and cycle-to-cycle (CTC) variabilities relevant magnitudes to be quantified and modeled. To accomplish this aim, robust and reliable parameter extraction methods must be employed. In this work, four different extraction methods were used at the production level (over all the 108 devices integrated on 200-mm wafers manufactured in the IHP 130-nm CMOS technology) in order to obtain the corresponding collection of forming, reset, and set switching voltages. The statistical analysis of the experimental data (mean and standard deviation (SD) values) was plotted by using heat maps, which provide a good summary of the whole data at a glance and, in addition, an easy manner to detect inhomogeneities in the fabrication process.}, language = {en} } @misc{PerezBoschQuesadaMistroniJiaetal., author = {Perez-Bosch Quesada, Emilio and Mistroni, Alberto and Jia, Ruolan and Dorai Swamy Reddy, Keerthi and Reichmann, Felix and Castan, Helena and Due{\~n}as, Salvador and Wenger, Christian and Perez, Eduardo}, title = {Forming and resistive switching of HfO₂-based RRAM devices at cryogenic temperature}, series = {IEEE Electron Device Letters}, volume = {45}, journal = {IEEE Electron Device Letters}, number = {12}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, issn = {0741-3106}, doi = {10.1109/LED.2024.3485873}, pages = {2391 -- 2394}, abstract = {Reliable data storage technologies able to operate at cryogenic temperatures are critical to implement scalable quantum computers and develop deep-space exploration systems, among other applications. Their scarce availability is pushing towards the development of emerging memories that can perform such storage in a non-volatile fashion. Resistive Random-Access Memories (RRAM) have demonstrated their switching capabilities down to 4K. However, their operability at lower temperatures still remain as a challenge. In this work, we demonstrate for the first time the forming and resistive switching capabilities of CMOS-compatible RRAM devices at 1.4K. The HfO2-based devices are deployed following an array of 1-transistor-1-resistor (1T1R) cells. Their switching performance at 1.4K was also tested in the multilevel-cell (MLC) approach, storing up to 4 resistance levels per cell.}, language = {en} } @misc{UhlmannRizziWenetal., author = {Uhlmann, Max and Rizzi, Tommaso and Wen, Jianan and P{\´e}rez-Bosch Quesada, Emilio and Al Beattie, Bakr and Ochs, Karlheinz and P{\´e}rez, Eduardo and Ostrovskyy, Philip and Carta, Corrado and Wenger, Christian and Kahmen, Gerhard}, title = {LUT-based RRAM model for neural accelerator circuit simulation}, series = {Proceedings of the 18th ACM International Symposium on Nanoscale Architectures}, journal = {Proceedings of the 18th ACM International Symposium on Nanoscale Architectures}, publisher = {ACM}, address = {New York, NY, USA}, doi = {10.1145/3611315.3633273}, pages = {1 -- 6}, abstract = {Neural hardware accelerators have been proven to be energy-efficient when used to solve tasks which can be mapped into an artificial neural network (ANN) structure. Resistive random-access memories (RRAMs) are currently under investigation together with several different memristive devices as promising technologies to build such accelerators combined together with complementary metal-oxide semiconductor (CMOS)-technologies in integrated circuits (ICs). While many research groups are actively developing sophisticated physical-based representations to better understand the underlying phenomena characterizing these devices, not much work has been dedicated to exploit the trade-off between simulation time and accuracy in the definition of low computational demanding models suitable to be used at many abstraction layers. Indeed, the design of complex mixed-signal systems as a neural hardware accelerators requires frequent interaction between the application- and the circuit-level that can be enabled only with the support of accurate and fast-simulating devices' models. In this work, we propose a solution to fill the aforementioned gap with a lookup table (LUT)-based Verilog-A model of IHP's 1-transistor-1-RRAM (1T1R) cell. In addition, the implementation challenges of conveying the communication between the abstract ANN simulation and the circuital analysis are tackled with a design flow for resistive neural hardware accelerators that features a custom Python wrapper. As a demonstration of the proposed design flow and 1T1R model, an ANN for the MNIST handwritten digit recognition task is assessed with the last layer verified in circuit simulation. The obtained recognition confidence intervals show a considerable discrepancy between the purely application-level PyTorch simulation and the proposed design flow which spans across the abstraction layers down to the circuital analysis.}, language = {en} } @misc{KloesBischoffLeiseetal., author = {Kloes, Alexander and Bischoff, Carl and Leise, Jakob and Perez-Bosch Quesada, Emilio and Wenger, Christian and P{\´e}rez, Eduardo}, title = {Stochastic switching of memristors and consideration in circuit simulation}, series = {Solid State Electronics}, volume = {201}, journal = {Solid State Electronics}, issn = {0038-1101}, doi = {10.1016/j.sse.2023.108606}, abstract = {We explore the stochastic switching of oxide-based memristive devices by using the Stanford model for circuit simulation. From measurements, the device-to-device (D2D) and cycle-to-cycle (C2C) statistical variation is extracted. In the low-resistive state (LRS) dispersion by D2D variability is dominant. In the high-resistive state (HRS) C2C dispersion becomes the main source of fluctuation. A statistical procedure for the extraction of parameters of the compact model is presented. Thereby, in a circuit simulation the typical D2D and C2C fluctuations of the current-voltage (I-V) characteristics can be emulated by extracting statistical parameters of key model parameters. The statistical distributions of the parameters are used in a Monte Carlo simulation to reproduce the I-V D2D and C2C dispersions which show a good agreement to the measured curves. The results allow the simulation of the on/off current variation for the design of memory cells or can be used to emulate the synaptic behavior of these devices in artificial neural networks realized by a crossbar array of memristors.}, language = {en} } @misc{PerezBoschQuesadaMahadevaiahRizzietal., author = {Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Rizzi, Tommaso and Wen, Jianan and Ulbricht, Markus and Krstic, Milos and Wenger, Christian and P{\´e}rez, Eduardo}, title = {Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing}, series = {IEEE Transactions on Electron Devices}, volume = {70}, journal = {IEEE Transactions on Electron Devices}, number = {4}, issn = {0018-9383}, doi = {10.1109/TED.2023.3244509}, pages = {2009 -- 2014}, abstract = {Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of 8x8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices' nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems.}, language = {en} } @misc{DerschPerezBoschQuesadaPerezetal., author = {Dersch, Nadine and Perez-Bosch Quesada, Emilio and P{\´e}rez, Eduardo and Wenger, Christian and Roemer, Christian and Schwarz, Mike and Kloes, Alexander}, title = {Efficient circuit simulation of a memristive crossbar array with synaptic weight variability}, series = {Solid State Electronics}, volume = {209}, journal = {Solid State Electronics}, issn = {0038-1101}, doi = {10.1016/j.sse.2023.108760}, abstract = {In this paper, we present a method for highly-efficient circuit simulation of a hardware-based artificial neural network realized in a memristive crossbar array. The statistical variability of the devices is considered by a noise-based simulation technique. For the simulation of a crossbar array with 8 synaptic weights in Cadence Virtuoso the new approach shows a more than 200x speed improvement compared to a Monte Carlo approach, yielding the same results. In addition, first results of an ANN with more than 15,000 memristive devices classifying test data of the MNIST dataset are shown, for which the speed improvement is expected to be several orders of magnitude. Furthermore, the influence on the classification of parasitic resistances of the connection lines in the crossbar is shown.}, language = {en} } @misc{UhlmannPerezBoschQuesadaFritscheretal., author = {Uhlmann, Max and P{\´e}rez-Bosch Quesada, Emilio and Fritscher, Markus and P{\´e}rez, Eduardo and Schubert, Markus Andreas and Reichenbach, Marc and Ostrovskyy, Philip and Wenger, Christian and Kahmen, Gerhard}, title = {One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing}, series = {21st IEEE Interregional NEWCAS Conference (NEWCAS)}, journal = {21st IEEE Interregional NEWCAS Conference (NEWCAS)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-0024-6}, issn = {2474-9672}, doi = {10.1109/NEWCAS57931.2023.10198073}, pages = {5}, abstract = {The use of resistive random-access memory (RRAM) for in-memory computing (IMC) architectures has significantly improved the energy-efficiency of artificial neural networks (ANN) over the past years. Current RRAM-technologies are physically limited to a defined unambiguously distinguishable number of stable states and a maximum resistive value and are compatible with present complementary metal-oxide semiconductor (CMOS)-technologies. In this work, we improved the accuracy of current ANN models by using increased weight resolutions of memristive devices, combining two or more in-series RRAM cells, integrated in the back end of line (BEOL) of the CMOS process. Based on system level simulations, 1T2R devices were fabricated in IHP's 130nm SiGe:BiCMOS technology node, demonstrating an increased number of states. We achieved an increase in weight resolution from 3 bit in ITIR cells to 6.5 bit in our 1T2R cell. The experimental data of 1T2R devices gives indications for the performance and energy-efficiency improvement in ITNR arrays for ANN applications.}, language = {en} } @misc{MaldonadoCantudoPerezetal., author = {Maldonado, David and Cantudo, Antonio and P{\´e}rez, Eduardo and Romero-Zaliz, Rocio and Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {TiN/Ti/HfO2/TiN Memristive Devices for Neuromorphic Computing: From Synaptic Plasticity to Stochastic Resonance}, series = {Frontiers in Neuroscience}, volume = {17}, journal = {Frontiers in Neuroscience}, issn = {1662-4548}, doi = {10.3389/fnins.2023.1271956}, abstract = {We characterize TiN/Ti/HfO2/TiN memristive devices for neuromorphic computing. We analyze different features that allow the devices to mimic biological synapses and present the models to reproduce analytically some of the data measured. In particular, we have measured the spike timing dependent plasticity behavior in our devices and later on we have modeled it. The spike timing dependent plasticity model was implemented as the learning rule of a spiking neural network that was trained to recognize the MNIST dataset. Variability is implemented and its influence on the network recognition accuracy is considered accounting for the number of neurons in the network and the number of training epochs. Finally, stochastic resonance is studied as another synaptic feature.It is shown that this effect is important and greatly depends on the noise statistical characteristics.}, language = {en} } @misc{PerezBoschQuesadaRizziGuptaetal., author = {Perez-Bosch Quesada, Emilio and Rizzi, Tommaso and Gupta, Aditya and Mahadevaiah, Mamathamba Kalishettyhalli and Schubert, Andreas and Pechmann, Stefan and Jia, Ruolan and Uhlmann, Max and Hagelauer, Amelie and Wenger, Christian and P{\´e}rez, Eduardo}, title = {Multi-Level Programming on Radiation-Hard 1T1R Memristive Devices for In-Memory Computing}, series = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, journal = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-0240-0}, doi = {10.1109/CDE58627.2023.10339525}, pages = {4}, abstract = {This work presents a quasi-static electrical characterization of 1-transistor-1-resistor memristive structures designed following hardness-by-design techniques integrated in the CMOS fabrication process to assure multi-level capabilities in harsh radiation environments. Modulating the gate voltage of the enclosed layout transistor connected in series with the memristive device, it was possible to achieve excellent switching capabilities from a single high resistance state to a total of eight different low resistance states (more than 3 bits). Thus, the fabricated devices are suitable for their integration in larger in-memory computing systems and in multi-level memory applications. Index Terms—radiation-hard, hardness-by-design, memristive devices, Enclosed Layout Transistor, in-memory computing}, language = {en} } @misc{PerezMaldonadoMahadevaiahetal., author = {P{\´e}rez, Eduardo and Maldonado, David and Mahadevaiah, Mamathamba Kalishettyhalli and Perez-Bosch Quesada, Emilio and Cantudo, Antonio and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {A comparison of resistive switching parameters for memristive devices with HfO2 monolayers and Al2O3/HfO2 bilayers at the wafer scale}, series = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, journal = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-0240-0}, doi = {10.1109/CDE58627.2023.10339417}, pages = {5}, abstract = {Memristive devices integrated in 200 mm wafers manufactured in 130 nm CMOS technology with two different dielectrics, namely, a HfO2 monolayer and an Al2O3/HfO2 bilayer, have been measured. The cycle-to-cycle (C2C) and device-todevice (D2D) variability have been analyzed at the wafer scale using different numerical methods to extract the set (Vset) and reset (Vreset) voltages. Some interesting differences between both technologies were found in terms of switching characteristics}, language = {en} }