@misc{KloesBischoffLeiseetal., author = {Kloes, Alexander and Bischoff, Carl and Leise, Jakob and Perez-Bosch Quesada, Emilio and Wenger, Christian and P{\´e}rez, Eduardo}, title = {Stochastic switching of memristors and consideration in circuit simulation}, series = {Solid State Electronics}, volume = {201}, journal = {Solid State Electronics}, issn = {0038-1101}, doi = {10.1016/j.sse.2023.108606}, abstract = {We explore the stochastic switching of oxide-based memristive devices by using the Stanford model for circuit simulation. From measurements, the device-to-device (D2D) and cycle-to-cycle (C2C) statistical variation is extracted. In the low-resistive state (LRS) dispersion by D2D variability is dominant. In the high-resistive state (HRS) C2C dispersion becomes the main source of fluctuation. A statistical procedure for the extraction of parameters of the compact model is presented. Thereby, in a circuit simulation the typical D2D and C2C fluctuations of the current-voltage (I-V) characteristics can be emulated by extracting statistical parameters of key model parameters. The statistical distributions of the parameters are used in a Monte Carlo simulation to reproduce the I-V D2D and C2C dispersions which show a good agreement to the measured curves. The results allow the simulation of the on/off current variation for the design of memory cells or can be used to emulate the synaptic behavior of these devices in artificial neural networks realized by a crossbar array of memristors.}, language = {en} } @misc{PerezBoschQuesadaMahadevaiahRizzietal., author = {Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Rizzi, Tommaso and Wen, Jianan and Ulbricht, Markus and Krstic, Milos and Wenger, Christian and P{\´e}rez, Eduardo}, title = {Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing}, series = {IEEE Transactions on Electron Devices}, volume = {70}, journal = {IEEE Transactions on Electron Devices}, number = {4}, issn = {0018-9383}, doi = {10.1109/TED.2023.3244509}, pages = {2009 -- 2014}, abstract = {Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of 8x8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices' nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems.}, language = {en} } @misc{DerschPerezBoschQuesadaPerezetal., author = {Dersch, Nadine and Perez-Bosch Quesada, Emilio and P{\´e}rez, Eduardo and Wenger, Christian and Roemer, Christian and Schwarz, Mike and Kloes, Alexander}, title = {Efficient circuit simulation of a memristive crossbar array with synaptic weight variability}, series = {Solid State Electronics}, volume = {209}, journal = {Solid State Electronics}, issn = {0038-1101}, doi = {10.1016/j.sse.2023.108760}, abstract = {In this paper, we present a method for highly-efficient circuit simulation of a hardware-based artificial neural network realized in a memristive crossbar array. The statistical variability of the devices is considered by a noise-based simulation technique. For the simulation of a crossbar array with 8 synaptic weights in Cadence Virtuoso the new approach shows a more than 200x speed improvement compared to a Monte Carlo approach, yielding the same results. In addition, first results of an ANN with more than 15,000 memristive devices classifying test data of the MNIST dataset are shown, for which the speed improvement is expected to be several orders of magnitude. Furthermore, the influence on the classification of parasitic resistances of the connection lines in the crossbar is shown.}, language = {en} } @misc{UhlmannPerezBoschQuesadaFritscheretal., author = {Uhlmann, Max and P{\´e}rez-Bosch Quesada, Emilio and Fritscher, Markus and P{\´e}rez, Eduardo and Schubert, Markus Andreas and Reichenbach, Marc and Ostrovskyy, Philip and Wenger, Christian and Kahmen, Gerhard}, title = {One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing}, series = {21st IEEE Interregional NEWCAS Conference (NEWCAS)}, journal = {21st IEEE Interregional NEWCAS Conference (NEWCAS)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-0024-6}, issn = {2474-9672}, doi = {10.1109/NEWCAS57931.2023.10198073}, pages = {5}, abstract = {The use of resistive random-access memory (RRAM) for in-memory computing (IMC) architectures has significantly improved the energy-efficiency of artificial neural networks (ANN) over the past years. Current RRAM-technologies are physically limited to a defined unambiguously distinguishable number of stable states and a maximum resistive value and are compatible with present complementary metal-oxide semiconductor (CMOS)-technologies. In this work, we improved the accuracy of current ANN models by using increased weight resolutions of memristive devices, combining two or more in-series RRAM cells, integrated in the back end of line (BEOL) of the CMOS process. Based on system level simulations, 1T2R devices were fabricated in IHP's 130nm SiGe:BiCMOS technology node, demonstrating an increased number of states. We achieved an increase in weight resolution from 3 bit in ITIR cells to 6.5 bit in our 1T2R cell. The experimental data of 1T2R devices gives indications for the performance and energy-efficiency improvement in ITNR arrays for ANN applications.}, language = {en} } @misc{MaldonadoCantudoPerezetal., author = {Maldonado, David and Cantudo, Antonio and P{\´e}rez, Eduardo and Romero-Zaliz, Rocio and Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {TiN/Ti/HfO2/TiN Memristive Devices for Neuromorphic Computing: From Synaptic Plasticity to Stochastic Resonance}, series = {Frontiers in Neuroscience}, volume = {17}, journal = {Frontiers in Neuroscience}, issn = {1662-4548}, doi = {10.3389/fnins.2023.1271956}, abstract = {We characterize TiN/Ti/HfO2/TiN memristive devices for neuromorphic computing. We analyze different features that allow the devices to mimic biological synapses and present the models to reproduce analytically some of the data measured. In particular, we have measured the spike timing dependent plasticity behavior in our devices and later on we have modeled it. The spike timing dependent plasticity model was implemented as the learning rule of a spiking neural network that was trained to recognize the MNIST dataset. Variability is implemented and its influence on the network recognition accuracy is considered accounting for the number of neurons in the network and the number of training epochs. Finally, stochastic resonance is studied as another synaptic feature.It is shown that this effect is important and greatly depends on the noise statistical characteristics.}, language = {en} } @misc{PerezBoschQuesadaRizziGuptaetal., author = {Perez-Bosch Quesada, Emilio and Rizzi, Tommaso and Gupta, Aditya and Mahadevaiah, Mamathamba Kalishettyhalli and Schubert, Andreas and Pechmann, Stefan and Jia, Ruolan and Uhlmann, Max and Hagelauer, Amelie and Wenger, Christian and P{\´e}rez, Eduardo}, title = {Multi-Level Programming on Radiation-Hard 1T1R Memristive Devices for In-Memory Computing}, series = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, journal = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-0240-0}, doi = {10.1109/CDE58627.2023.10339525}, pages = {4}, abstract = {This work presents a quasi-static electrical characterization of 1-transistor-1-resistor memristive structures designed following hardness-by-design techniques integrated in the CMOS fabrication process to assure multi-level capabilities in harsh radiation environments. Modulating the gate voltage of the enclosed layout transistor connected in series with the memristive device, it was possible to achieve excellent switching capabilities from a single high resistance state to a total of eight different low resistance states (more than 3 bits). Thus, the fabricated devices are suitable for their integration in larger in-memory computing systems and in multi-level memory applications. Index Terms—radiation-hard, hardness-by-design, memristive devices, Enclosed Layout Transistor, in-memory computing}, language = {en} } @misc{PerezMaldonadoMahadevaiahetal., author = {P{\´e}rez, Eduardo and Maldonado, David and Mahadevaiah, Mamathamba Kalishettyhalli and Perez-Bosch Quesada, Emilio and Cantudo, Antonio and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {A comparison of resistive switching parameters for memristive devices with HfO2 monolayers and Al2O3/HfO2 bilayers at the wafer scale}, series = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, journal = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-0240-0}, doi = {10.1109/CDE58627.2023.10339417}, pages = {5}, abstract = {Memristive devices integrated in 200 mm wafers manufactured in 130 nm CMOS technology with two different dielectrics, namely, a HfO2 monolayer and an Al2O3/HfO2 bilayer, have been measured. The cycle-to-cycle (C2C) and device-todevice (D2D) variability have been analyzed at the wafer scale using different numerical methods to extract the set (Vset) and reset (Vreset) voltages. Some interesting differences between both technologies were found in terms of switching characteristics}, language = {en} } @misc{UhlmannRizziWenetal., author = {Uhlmann, Max and Rizzi, Tommaso and Wen, Jianan and Quesada, Emilio P{\´e}rez-Bosch and Beattie, Bakr Al and Ochs, Karlheinz and P{\´e}rez, Eduardo and Ostrovskyy, Philip and Carta, Corrado and Wenger, Christian and Kahmen, Gerhard}, title = {End-to-end design flow for resistive neural accelerators}, series = {IEEE transactions on computer-aided design of integrated circuits and systems}, journal = {IEEE transactions on computer-aided design of integrated circuits and systems}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {0278-0070}, doi = {10.1109/TCAD.2025.3597237}, pages = {1 -- 5}, abstract = {Neural hardware accelerators have demonstrated notable energy efficiency in tackling tasks, which can be adapted to artificial neural network (ANN) structures. Research is currently directed towards leveraging resistive random-access memories (RRAMs) among various memristive devices. In conjunction with complementary metal-oxide semiconductor (CMOS) technologies within integrated circuits (ICs), RRAM devices are used to build such neural accelerators. In this study, we present a neural accelerator hardware design and verification flow, which uses a lookup table (LUT)-based Verilog-A model of IHP's one-transistor-one-RRAM (1T1R) cell. In particular, we address the challenges of interfacing between abstract ANN simulations and circuit analysis by including a tailored Python wrapper into the design process for resistive neural hardware accelerators. To demonstrate our concept, the efficacy of the proposed design flow, we evaluate an ANN for the MNIST handwritten digit recognition task, as well as for the CIFAR-10 image recognition task, with the last layer verified through circuit simulation. Additionally, we implement different versions of a 1T1R model, based on quasi-static measurement data, providing insights on the effect of conductance level spacing and device-to-device variability. The circuit simulations tackle both schematic and physical layout assessment. The resulting recognition accuracies exhibit significant differences between the purely application-level PyTorch simulation and our proposed design flow, highlighting the relevance of circuit-level validation for the design of neural hardware accelerators.}, language = {en} } @misc{PerezMaldonadoAcaletal., author = {P{\´e}rez, Eduardo and Maldonado, David and Acal, Christian and Ruiz-Castro, Juan Eloy and Aguilera, Ana Mar{\´i}a and Jimenez-Molinos, Francisco and Roldan, Juan Bautista and Wenger, Christian}, title = {Advanced Temperature Dependent Statistical Analysis of Forming Voltage Distributions for Three Different HfO2-Based RRAM Technologies}, series = {Solid State Electronics}, volume = {176}, journal = {Solid State Electronics}, issn = {0038-1101}, pages = {6}, abstract = {In this work, voltage distributions of forming operations are analyzed by using an advanced statistical approach based on phase-type distributions (PHD). The experimental data were collected from batches of 128 HfO2-based RRAM devices integrated in 4-kbit arrays. Three di erent switching oxides, namely, polycrystalline HfO2, amorphous HfO2, and Al-doped HfO2, were tested in the temperature range from -40 to 150 oC. The variability of forming voltages has been usually studied by using the Weibull distribution (WD). However, the performance of the PHD analysis demonstrated its ability to better model this crucial operation. The capacity of the PHD to reproduce the experimental data has been validated by means of the Kolmogorov-Smirnov test, while the WD failed in many of the cases studied. In addition, PHD allows to extract information about intermediate probabilistic states that occur in the forming process and the transition probabilities between them; in this manner, we can deepen on the conductive lament formation physics. In particular, the number of intermediate states can be related to the device variability.}, language = {en} } @misc{RomeroZalizPerezJimenezMolinosetal., author = {Romero-Zaliz, Roc{\´i}o and P{\´e}rez, Eduardo and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {Study of Quantized Hardware Deep Neural Networks Based on Resistive Switching Devices, Conventional versus Convolutional Approaches}, series = {Electronics (MDPI)}, volume = {10}, journal = {Electronics (MDPI)}, number = {3}, issn = {2079-9292}, doi = {10.3390/electronics10030346}, pages = {14}, abstract = {A comprehensive analysis of two types of artificial neural networks (ANN) is performed to assess the influence of quantization on the synaptic weights. Conventional multilayer-perceptron (MLP) and convolutional neural networks (CNN) have been considered by changing their features in the training and inference contexts, such as number of levels in the quantization process, the number of hidden layers on the network topology, the number of neurons per hidden layer, the image databases, the number of convolutional layers, etc. A reference technology based on 1T1R structures with bipolar memristors including HfO2 dielectrics was employed, accounting for different multilevel schemes and the corresponding conductance quantization algorithms. The accuracy of the image recognition processes was studied in depth. This type of studies are essential prior to hardware implementation of neural networks. The obtained results support the use of CNNs for image domains. This is linked to the role played by convolutional layers at extracting image features and reducing the data complexity. In this case, the number of synaptic weights can be reduced in comparison to conventional MLPs.}, language = {en} } @misc{SoltaniZarrinZahariMahadevaiahetal., author = {Soltani Zarrin, Pouya and Zahari, Finn and Mahadevaiah, Mamathamba Kalishettyhalli and P{\´e}rez, Eduardo and Kohlstedt, Hermann and Wenger, Christian}, title = {Neuromorphic on‑chip recognition of saliva samples of COPD and healthy controls using memristive devices}, series = {Scientific Reports}, volume = {10}, journal = {Scientific Reports}, issn = {2045-2322}, doi = {10.1038/s41598-020-76823-7}, abstract = {Chronic Obstructive Pulmonary Disease (COPD) is a life-threatening lung disease, affecting millions of people worldwide. Implementation of Machine Learning (ML) techniques is crucial for the effective management of COPD in home-care environments. However, shortcomings of cloud-based ML tools in terms of data safety and energy efficiency limit their integration with low-power medical devices. To address this, energy efficient neuromorphic platforms can be used for the hardware-based implementation of ML methods. Therefore, a memristive neuromorphic platform is presented in this paper for the on-chip recognition of saliva samples of COPD patients and healthy controls. The results of its performance evaluations showed that the digital neuromorphic chip is capable of recognizing unseen COPD samples with accuracy and sensitivity values of 89\% and 86\%, respectively. Integration of this technology into personalized healthcare devices will enable the better management of chronic diseases such as COPD.}, language = {en} } @misc{ZanottiPuglisiMiloetal., author = {Zanotti, Tommaso and Puglisi, Francesco Maria and Milo, Valerio and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Ossorio, {\´O}scar G. and Wenger, Christian and Pavan, Paolo and Olivo, Piero and Ielmini, Daniele}, title = {Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays}, series = {IEEE Transactions on Electron Devices}, volume = {67}, journal = {IEEE Transactions on Electron Devices}, number = {11}, issn = {0018-9383}, doi = {10.1109/TED.2020.3025271}, pages = {4611 -- 4615}, abstract = {Logic-in-memory (LiM) circuits based on resistive random access memory (RRAM) devices and the material implication logic are promising candidates for the development of low-power computing devices that could fulfill the growing demand of distributed computing systems. However, these circuits are affected by many reliability challenges that arise from device nonidealities (e.g., variability) and the characteristics of the employed circuit architecture. Thus, an accurate investigation of the variability at the array level is needed to evaluate the reliability and performance of such circuit architectures. In this work, we explore the reliability and performance of smart IMPLY (SIMPLY) (i.e., a recently proposed LiM architecture with improved reliability and performance) on two 4-kb RRAM arrays based on different resistive switching oxides integrated in the back end of line (BEOL) of the 0.25- μm BiCMOS process. We analyze the tradeoff between reliability and energy consumption of SIMPLY architecture by exploiting the results of an extensive array-level variability characterization of the two technologies. Finally, we study the worst case performance of a full adder implemented with the SIMPLY architecture and benchmark it on the analogous CMOS implementation.}, language = {en} } @misc{ZahariPerezMahadevaiahetal., author = {Zahari, Finn and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Kohlstedt, Hermann and Wenger, Christian and Ziegler, Martin}, title = {Analogue pattern recognition with stochastic switching binary CMOS‑integrated memristive devices}, series = {Scientific Reports}, volume = {10}, journal = {Scientific Reports}, issn = {2045-2322}, doi = {10.1038/s41598-020-71334-x}, pages = {15}, abstract = {Biological neural networks outperform todays computer technology in terms of power consumption and computing speed when associative tasks, like pattern recognition, are to be solved. The analogue and massive parallel in-memory computing in biology differs strongly with conventional transistor electronics using the von Neumann architecture. Therefore, novel bio-inspired computing architectures are recently highly investigated in the area of neuromorphic computing. Here, memristive devices, which serve as non-volatile resistive memory, are used to emulate the plastic behaviour of biological synapses. In particular, CMOS integrated resistive random access memory (RRAM) devices are promising candidates to extend conventional CMOS technology in neuromorphic systems. However, dealing with the inherent stochasticity of the resistive switching effect can be challenging for network performance. In this work, the probabilistic switching is exploited to emulate stochastic plasticity with fully CMOS integrated binary RRAM devices. Two different RRAM technologies with different device variabilities are investigated in detail and their use in a stochastic artificial neural network (StochANN) to solve the MINST pattern recognition task is examined. A mixed-signal implementation with hardware synapses and software neurons as well as numerical simulations show the proposed concept of stochastic computing is able to handle analogue data with binary memory cells.}, language = {en} } @misc{PerezOssorioDuenasetal., author = {P{\´e}rez, Eduardo and Ossorio, {\´O}scar G. and Due{\~n}as, Salvador and Cast{\´a}n, Helena and Garc{\´i}a, Hector and Wenger, Christian}, title = {Programming Pulse Width Assessment for Reliable and Low-Energy Endurance Performance in Al:HfO2-Based RRAM Arrays}, series = {Electronics (MDPI)}, volume = {9}, journal = {Electronics (MDPI)}, number = {5}, issn = {2079-9292}, doi = {10.3390/electronics9050864}, abstract = {A crucial step in order to achieve fast and low-energy switching operations in resistive random access memory (RRAM) memories is the reduction of the programming pulse width. In this study, the incremental step pulse with verify algorithm (ISPVA) was implemented by using different pulse widths between 10 μ s and 50 ns and assessed on Al-doped HfO 2 4 kbit RRAM memory arrays. The switching stability was assessed by means of an endurance test of 1k cycles. Both conductive levels and voltages needed for switching showed a remarkable good behavior along 1k reset/set cycles regardless the programming pulse width implemented. Nevertheless, the distributions of voltages as well as the amount of energy required to carry out the switching operations were definitely affected by the value of the pulse width. In addition, the data retention was evaluated after the endurance analysis by annealing the RRAM devices at 150 °C along 100 h. Just an almost negligible increase on the rate of degradation of about 1 μ A at the end of the 100 h of annealing was reported between those samples programmed by employing a pulse width of 10 μ s and those employing 50 ns. Finally, an endurance performance of 200k cycles without any degradation was achieved on 128 RRAM devices by using programming pulses of 100 ns width}, language = {en} }