@misc{MiloAnzaloneZambellietal., author = {Milo, Valerio and Anzalone, Francesco and Zambelli, Cristian and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Ossorio, {\´O}scar G. and Olivo, Piero and Wenger, Christian and Ielmini, Daniele}, title = {Optimized programming algorithms for multilevel RRAM in hardware neural networks}, series = {IEEE International Reliability Physics Symposium (IRPS), 2021}, journal = {IEEE International Reliability Physics Symposium (IRPS), 2021}, isbn = {978-1-7281-6894-4}, issn = {1938-1891}, doi = {10.1109/IRPS46558.2021.9405119}, abstract = {A key requirement for RRAM in neural network accelerators with a large number of synaptic parameters is the multilevel programming. This is hindered by resistance imprecision due to cycle-to-cycle and device-to-device variations. Here, we compare two multilevel programming algorithms to minimize resistance variations in a 4-kbit array of HfO 2 RRAM. We show that gate-based algorithms have the highest reliability. The optimized scheme is used to implement a neural network with 9-level weights, achieving 91.5\% (vs. software 93.27\%) in MNIST recognition.}, language = {en} } @misc{BaroniZambelliOlivoetal., author = {Baroni, Andrea and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele}, title = {Tackling the Low Conductance State Drift through Incremental Reset and Verify in RRAM Arrays}, series = {2021 IEEE International Integrated Reliability Workshop (IIRW), South Lake Tahoe, CA, USA, 10 December 2021}, journal = {2021 IEEE International Integrated Reliability Workshop (IIRW), South Lake Tahoe, CA, USA, 10 December 2021}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {978-1-6654-1794-5}, issn = {2374-8036}, doi = {10.1109/IIRW53245.2021.9635613}, pages = {5}, abstract = {Resistive switching memory (RRAM) is a promising technology for highly efficient computing scenarios. RRAM arrays enabled the acceleration of neural networks for artificial intelligence and the creation of In-Memory Computing circuits. However, the arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation in those applications. Among those, one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are fundamental for an accurate Multi-level conductance operation. In this work, we tackle the issue by developing an Incremental Reset and Verify technique showing enhanced variability and reliability features compared with a traditional refresh-based approach.}, language = {en} } @misc{GlukhovMiloBaronietal., author = {Glukhov, Artem and Milo, Valerio and Baroni, Andrea and Lepri, Nicola and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele}, title = {Statistical model of program/verify algorithms in resistive-switching memories for in-memory neural network accelerators}, series = {2022 IEEE International Reliability Physics Symposium (IRPS)}, journal = {2022 IEEE International Reliability Physics Symposium (IRPS)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {978-1-6654-7950-9}, issn = {2473-2001}, doi = {10.1109/IRPS48227.2022.9764497}, pages = {3C.3-1 -- 3C.3-7}, abstract = {Resistive-switching random access memory (RRAM) is a promising technology for in-memory computing (IMC) to accelerate training and inference of deep neural networks (DNNs). This work presents the first physics-based statistical model describing (i) multilevel RRAM device program/verify (PV) algorithms by controlled set transition, (ii) the stochastic cycle-to-cycle (C2C) and device-to-device (D2D) variations within the array, and (iii) the impact of such imprecisions on the accuracy of DNN accelerators. The model can handle the full chain from RRAM materials/device parameters to the DNN performance, thus providing a valuable tool for device/circuit codesign of hardware DNN accelerators.}, language = {en} } @misc{GlukhovLepriMiloetal., author = {Glukhov, Artem and Lepri, Nicola and Milo, Valerio and Baroni, Andrea and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele}, title = {End-to-end modeling of variability-aware neural networks based on resistive-switching memory arrays}, series = {Proc. 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2022)}, journal = {Proc. 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2022)}, doi = {10.1109/VLSI-SoC54400.2022.9939653}, pages = {1 -- 5}, abstract = {Resistive-switching random access memory (RRAM) is a promising technology that enables advanced applications in the field of in-memory computing (IMC). By operating the memory array in the analogue domain, RRAM-based IMC architectures can dramatically improve the energy efficiency of deep neural networks (DNNs). However, achieving a high inference accuracy is challenged by significant variation of RRAM conductance levels, which can be compensated by (i) advanced programming techniques and (ii) variability-aware training (VAT) algorithms. In both cases, however, detailed knowledge and accurate physics-based statistical models of RRAM are needed to develop programming and VAT methodologies. This work presents an end-to-end approach to the development of highly-accurate IMC circuits with RRAM, encompassing the device modeling, the precise programming algorithm, and the VAT simulations to maximize the DNN classification accuracy in presence of conductance variations.}, language = {en} }