@misc{NitschRatzkePozarowskaetal.,
author = {Nitsch, Paul-G. and Ratzke, Markus and Pozarowska, Emilia and Flege, Jan Ingo and Alvarado Chavarin, Carlos and Wenger, Christian and Fischer, Inga Anita},
title = {Deposition of reduced ceria thin films by reactive magnetron sputtering for the development of a resistive gas sensor},
series = {Verhandlungen der DPG, Berlin 2024},
journal = {Verhandlungen der DPG, Berlin 2024},
publisher = {Deutsche Physikalische Gesellschaft},
address = {Bad Honnef},
issn = {0420-0195},
abstract = {The use of cerium oxide for hydrogen sensing is limited by the low electrical conductivity of layers deposited from a ceria target. To increase the electrical conductivity, partially reduced cerium oxide layers were obtained from a metallic cerium target by reactive magnetron sputtering. The proportions of the oxidation states Ce3+, present in reduced species, and Ce4+, present in fully oxidized species, were determined by ex-situ XPS. For electrical characterization, films were deposited on planarized tungsten finger electrodes. IV curves were measured over several days to investigate possible influences of oxygen and humidity on electrical conductivity. The morphological stability of the layers under ambient conditions was investigated by microscopical methods. The XPS results show a significant amount of Ce3+ in the layers. The electrical conductivity of as-grown samples is several orders of magnitude higher than that of samples grown from a ceria target. However, the conductivity decreases over time, indicating an oxidation of the layers. The surface morphology of the samples was found to be changing drastically within days, leading to partial delamination.},
language = {en}
}
@misc{StrobelAlvaradoChavarinKnautetal.,
author = {Strobel, Carsten and Alvarado Chavarin, Carlos and Knaut, Martin and V{\"o}lkel, Sandra and Albert, Matthias and Hiess, Andre and Max, Benjamin and Wenger, Christian and Kirchner, Robert and Mikolajick, Thomas},
title = {High Gain Graphene Based Hot Electron Transistor with Record High Saturated Output Current Density},
series = {Advanced Electronic Materials},
volume = {10},
journal = {Advanced Electronic Materials},
number = {2},
issn = {2199-160X},
doi = {10.1002/aelm.202300624},
abstract = {Hot electron transistors (HETs) represent an exciting frontier in semiconductor technology, holding the promise of high-speed and high-frequency electronics. With the exploration of two-dimensional materials such as graphene and new device architectures, HETs are poised to revolutionize the landscape of modern electronics. This study highlights a novel HET structure with a record output current density of 800 A/cm² and a high current gain α, fabricated using a scalable fabrication approach. The HET structure comprises two-dimensional hexagonal boron nitride (hBN) and graphene layers wet transferred to a germanium substrate. The combination of these materials results in exceptional performance, particularly in terms of the highly saturated output current density. The scalable fabrication scheme used to produce the HET opens up opportunities for large-scale manufacturing. This breakthrough in HET technology holds promise for advanced electronic applications, offering high current capabilities in a practical and manufacturable device.},
language = {en}
}
@misc{PechmannPerezWengeretal.,
author = {Pechmann, Stefan and P{\´e}rez, Eduardo and Wenger, Christian and Hagelauer, Amelie},
title = {A current mirror Based read circuit design with multi-level capability for resistive switching deviceb},
series = {2024 International Conference on Electronics, Information, and Communication (ICEIC)},
journal = {2024 International Conference on Electronics, Information, and Communication (ICEIC)},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
isbn = {979-8-3503-7188-8},
issn = {2767-7699},
doi = {10.1109/ICEIC61013.2024.10457188},
pages = {4},
abstract = {This paper presents a read circuit design for resistive memory cells based on current mirrors. The circuit utilizes high-precision current mirrors and reference cells to determine the state of resistive memory using comparators. It offers a high degree in adaptability in terms of both resistance range and number of levels. Special emphasis was put on device protection to prevent accidental programming of the memory during read operations. The realized circuit can resolve eight states with a resolution of up to 1 k Ω, realizing a digitization of the analog memory information. Furthermore, the integration in a complete memory macro is shown. The circuit was realized in a 130 nm-process but can easily be adapted to other processes and resistive memory technologies.},
language = {en}
}
@misc{NikiruyPerezBaronietal.,
author = {Nikiruy, Kristina and P{\´e}rez, Eduardo and Baroni, Andrea and Dorai Swamy Reddy, Keerthi and Pechmann, Stefan and Wenger, Christian and Ziegler, Martin},
title = {Blooming and pruning: learning from mistakes with memristive synapses},
series = {Scientific Reports},
volume = {14},
journal = {Scientific Reports},
number = {1},
issn = {2045-2322},
doi = {10.1038/s41598-024-57660-4},
abstract = {AbstractBlooming and pruning is one of the most important developmental mechanisms of the biological brain in the first years of life, enabling it to adapt its network structure to the demands of the environment. The mechanism is thought to be fundamental for the development of cognitive skills. Inspired by this, Chialvo and Bak proposed in 1999 a learning scheme that learns from mistakes by eliminating from the initial surplus of synaptic connections those that lead to an undesirable outcome. Here, this idea is implemented in a neuromorphic circuit scheme using CMOS integrated HfO2-based memristive devices. The implemented two-layer neural network learns in a self-organized manner without positive reinforcement and exploits the inherent variability of the memristive devices. This approach provides hardware, local, and energy-efficient learning. A combined experimental and simulation-based parameter study is presented to find the relevant system and device parameters leading to a compact and robust memristive neuromorphic circuit that can handle association tasks.},
language = {en}
}
@inproceedings{WenVargasZhuetal.,
author = {Wen, Jianan and Vargas, Fabian Luis and Zhu, Fukun and Reiser, Daniel and Baroni, Andrea and Fritscher, Markus and P{\´e}rez, Eduardo and Reichenbach, Marc and Wenger, Christian and Krstic, Milos},
title = {Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment},
series = {2024 IEEE 25th Latin American Test Symposium (LATS)},
booktitle = {2024 IEEE 25th Latin American Test Symposium (LATS)},
publisher = {IEEE},
doi = {10.1109/LATS62223.2024.10534601},
pages = {6},
abstract = {Emerging device technologies such as resistive RAM (RRAM) are increasingly recognized in enhancing system performance, particularly in applications demanding extensive vector-matrix multiplications (VMMs) with high parallelism. However, a significant limitation in current electronics design automation (EDA) tools is their lack of support for rapid prototyping, design space exploration, and the integration of inherent process-dependent device variability into system-level simulations, which is essential for assessing system reliability. To address this gap, we introduce a field-programmable gate array (FPGA) based emulation approach for RRAM crossbars featuring cycle-accurate emulations in real time without relying on complex device models. Our approach is based on pre-generated look-up tables (LUTs) to accurately represent the RRAM device behavior. To efficiently model the device variability at the system level, we propose using the multivariate kernel density estimation (KDE) method to augment the measured RRAM data. The proposed emulator allows precise latency determination for matrix mapping and computation operations. Meanwhile, by coupling with the NeuroSim framework, the corresponding energy consumption can be estimated. In addition to facilitating a range of in-depth system assessments, experimental results suggest a remarkable reduction of emulation time compared to the classic behavioral simulation.},
language = {en}
}
@misc{DoraiSwamyReddyPerezBaronietal.,
author = {Dorai Swamy Reddy, Keerthi and P{\´e}rez, Eduardo and Baroni, Andrea and Mahadevaiah, Mamathamba Kalishettyhalli and Marschmeyer, Steffen and Fraschke, Mirko and Lisker, Marco and Wenger, Christian and Mai, Andreas},
title = {Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance},
series = {The European Physical Journal B},
volume = {97},
journal = {The European Physical Journal B},
publisher = {Springer Science and Business Media LLC},
issn = {1434-6028},
doi = {10.1140/epjb/s10051-024-00821-1},
pages = {9},
abstract = {Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal-insulator-metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2 dielectric thickness from 8 nm to 5 nm. Additionally, 5\% Al-doped 4 nm HfO2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology.},
language = {en}
}
@misc{JiaPechmannMarkusetal.,
author = {Jia, Ruolan and Pechmann, Stefan and Markus, Fritscher and Wenger, Christian and Zhang, Lei and Hagelauer, Amelie},
title = {Soft-Error Analysis of RRAM 1T1R Compute-In-Memory Core for Artificial Neural Networks},
series = {2024 39th Conference on Design of Circuits and Integrated Systems (DCIS)},
journal = {2024 39th Conference on Design of Circuits and Integrated Systems (DCIS)},
publisher = {IEEE},
doi = {10.1109/DCIS62603.2024.10769203},
pages = {1 -- 5},
abstract = {This work analyses SEU-induced soft-errors in analog compute-in-memory cores using resistive random-access memory (RRAM) for artificial neural networks, where their bitcells utilize one-transistor-one-RRAM (1T1R) structure. This is modeled by combining the Stanford-PKU RRAM Model and the model of the radiation-induced photocurrent in access transistors. As results, this work derives the maximal RRAM crossbar size without occurring any logic flip and indicates the requirements for RRAM technology to achieve a SEU-resilient 1T1R compute-in memory cores.},
language = {en}
}
@misc{PerezBoschQuesadaMistroniJiaetal.,
author = {Perez-Bosch Quesada, Emilio and Mistroni, Alberto and Jia, Ruolan and Dorai Swamy Reddy, Keerthi and Reichmann, Felix and Castan, Helena and Due{\~n}as, Salvador and Wenger, Christian and Perez, Eduardo},
title = {Forming and resistive switching of HfO₂-based RRAM devices at cryogenic temperature},
series = {IEEE Electron Device Letters},
volume = {45},
journal = {IEEE Electron Device Letters},
number = {12},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
issn = {0741-3106},
doi = {10.1109/LED.2024.3485873},
pages = {2391 -- 2394},
abstract = {Reliable data storage technologies able to operate at cryogenic temperatures are critical to implement scalable quantum computers and develop deep-space exploration systems, among other applications. Their scarce availability is pushing towards the development of emerging memories that can perform such storage in a non-volatile fashion. Resistive Random-Access Memories (RRAM) have demonstrated their switching capabilities down to 4K. However, their operability at lower temperatures still remain as a challenge. In this work, we demonstrate for the first time the forming and resistive switching capabilities of CMOS-compatible RRAM devices at 1.4K. The HfO2-based devices are deployed following an array of 1-transistor-1-resistor (1T1R) cells. Their switching performance at 1.4K was also tested in the multilevel-cell (MLC) approach, storing up to 4 resistance levels per cell.},
language = {en}
}
@misc{WeisshauptSuergersBloosetal.,
author = {Weißhaupt, David and S{\"u}rgers, Christoph and Bloos, Dominik and Funk, Hannes Simon and Oehme, Michael and Fischer, Gerda and Schubert, Markus Andreas and Wenger, Christian and van Slageren, Joris and Fischer, Inga Anita and Schulze, J{\"o}rg},
title = {Lateral Mn5Ge3 spin-valve in contact with a high-mobility Ge two-dimensional hole gas},
series = {Semiconductor Science and Technology},
volume = {39},
journal = {Semiconductor Science and Technology},
number = {12},
publisher = {IOP Publishing},
issn = {0268-1242},
doi = {10.1088/1361-6641/ad8d06},
pages = {1 -- 10},
abstract = {Abstract Ge two-dimensional hole gases (2DHG) in strained modulation-doped quantum-wells represent a promising material platform for future spintronic applications due to their excellent spin transport properties and the theoretical possibility of efficient spin manipulation. Due to the continuous development of epitaxial growth recipes extreme high hole mobilities and low effective masses can be achieved, promising an efficient spin transport. Furthermore, the Ge 2DHG can be integrated in the well-established industrial complementary metal-oxide-semiconductor (CMOS) devices technology. However, efficient electrical spin injection into a Ge 2DHG—an essential prerequisite for the realization of spintronic devices—has not yet been demonstrated. In this work, we report the fabrication and low-temperature magnetoresistance (MR) measurements of a laterally structured Mn5Ge3/Ge 2DHG/ Mn5Ge3 device. The ferromagnetic Mn5Ge3 contacts are grown directly into the Ge quantum well by means of an interdiffusion process with a spacing of approximately 130 nm, forming a direct electrical contact between the ferromagnetic metal and the Ge 2DHG. Here, we report for the first time a clear MR signal for temperatures below 13 K possibly arising from successful spin injection into the high mobility Ge 2DHG. The results represent a step forward toward the realization of CMOS compatible spintronic devices based on a 2DHG.},
language = {en}
}
@misc{CapistaLukoseMajnoonetal.,
author = {Capista, Daniele and Lukose, Rasuole and Majnoon, Farnaz and Lisker, Marco and Wenger, Christian and Lukosius, Mindaugas},
title = {Optimization of the metal deposition process for the accurate estimation of Low Metal-Graphene Contact-Resistance},
series = {47th MIPRO ICT and Electronics Convention (MIPRO), 20-24 May 2024, Opatija, Croatia},
journal = {47th MIPRO ICT and Electronics Convention (MIPRO), 20-24 May 2024, Opatija, Croatia},
isbn = {979-8-3503-8250-1},
issn = {2623-8764},
doi = {10.1109/MIPRO60963.2024.10569895},
pages = {5},
language = {en}
}
@misc{MaldonadoCantudoSwamyReddyetal.,
author = {Maldonado, David and Cantudo, Antonio and Swamy Reddy, Keerthi Dorai and Pechmann, Stefan and Uhlmann, Max and Wenger, Christian and Roldan, Juan Bautista and P{\´e}rez, Eduardo},
title = {Influence of stop and gate voltage on resistive switching of 1T1R HfO2-based memristors, a modeling and variability analysis},
series = {Materials Science in Semiconductor Processing},
volume = {182},
journal = {Materials Science in Semiconductor Processing},
issn = {1873-4081},
doi = {10.1016/j.mssp.2024.108726},
pages = {9},
language = {en}
}
@misc{KostoTschammerMoralesetal.,
author = {Kosto, Yuliia and Tschammer, Rudi and Morales, Carlos and Henkel, Karsten and Flege, Jan Ingo and Ratzke, Markus and Fischer, Inga Anita and Costina, Ioan and Alvarado Chavarin, Carlos and Wenger, Christian},
title = {Rational design and development of room temperature hydrogen sensors compatible with CMOS technology: a necessary step for the coming renewable hydrogen economy},
series = {Proceedings of iCampus Conference Cottbus 2024},
journal = {Proceedings of iCampus Conference Cottbus 2024},
publisher = {AMA Service GmbH},
address = {Wunstorf},
isbn = {978-3-910600-00-3},
doi = {10.5162/iCCC2024/P21},
pages = {182 -- 185},
abstract = {The transition towards a new, renewable energy system based on green energy vectors, such as hydrogen, requires not only direct energy conversion and storage systems, but also the development of auxiliary components, such as highly sensitive hydrogen gas sensors integrated into mass devices that operate at ambient conditions. Despite the recent advances in nanostructured metal oxide thin films in terms of simple fabrication processes and compatibility with integrated circuits, high sensitivity, and short response/recovery times usually require the use of expensive noble metals or elevated tem-peratures (>250 ºC), which results in high power consumption and poor long-term stability. This article presents the first steps of the work on developing a novel resistive hydrogen gas sensor based on ultrathin cerium oxide films, compatible with complementary metal oxide semiconductor technology and capable of operating at room temperature. Here, we show a multidisciplinary bottom-up approach combining different work areas for the sensor development, such as sensor architecture, sensing mechanism and deposition strategy of the active layer, electrical contact design depending on the desired electrical output, and fast testing under controlled environments.},
language = {en}
}
@misc{VinuesaGarciaPerezetal.,
author = {Vinuesa, Guillermo and Garc{\´i}a, H{\´e}ctor and P{\´e}rez, Eduardo and Wenger, Christian and {\´I}{\~n}iguez de la Torre, Ignacio and Gonz{\´a}lez, Tom{\´a}s and Due{\~n}as, Salvador and Cast{\´a}n, Helena},
title = {On the asymmetry of Resistive Switching Transitions},
series = {Electronics},
volume = {13},
journal = {Electronics},
number = {13},
publisher = {MDPI},
issn = {2079-9292},
doi = {10.3390/electronics13132639},
pages = {11},
abstract = {In this study, the resistive switching phenomena in TiN/Ti/HfO2/Ti metal-insulator-metal stacks is investigated, mainly focusing on the analysis of set and reset transitions. The electrical measurements in a wide temperature range reveal that the switching transitions require less voltage (and thus, less energy) as temperature rises, with the reset process being much more temperature sensitive. The main conduction mechanism in both resistance states is Space-charge-limited Conduction, but the high conductivity state also shows Schottky emission, explaining its temperature dependence. Moreover, the temporal evolution of these transitions reveals clear differences between them, as their current transient response is completely different. While the set is sudden, the reset process development is clearly non-linear, closely resembling a sigmoid function. This asymmetry between switching processes is of extreme importance in the manipulation and control of the multi-level characteristics and has clear implications in the possible applications of resistive switching devices in neuromorphic computing.},
language = {en}
}
@misc{StrobelAlvaradoChavarinKnautetal.,
author = {Strobel, Carsten and Alvarado Chavarin, Carlos and Knaut, Martin and Albert, Matthias and Heinzig, Andr{\´e} and Gummadi, Likhith and Wenger, Christian and Mikolajick, Thomas},
title = {p-Type Schottky contacts for graphene adjustable-Barrier phototransistors},
series = {Nanomaterials},
volume = {14},
journal = {Nanomaterials},
number = {13},
editor = {Giannazzo, Filippo and Agnello, Simonpietro and Seravalli, Luca and Bondino, Federica},
publisher = {MDPI},
issn = {2079-4991},
doi = {10.3390/nano14131140},
abstract = {The graphene adjustable-barriers phototransistor is an attractive novel device for potential high speed and high responsivity dual-band photodetection. In this device, graphene is embedded between the semiconductors silicon and germanium. Both n-type and p-type Schottky contacts between graphene and the semiconductors are required for this device. While n-type Schottky contacts are widely investigated, reports about p-type Schottky contacts between graphene and the two involved semiconductors are scarce. In this study, we demonstrate a p-type Schottky contact between graphene and p-germanium. A clear rectification with on-off ratios of close to 10 3 (±5 V) and a distinct photoresponse at telecommunication wavelengths in the infrared are achieved. Further, p-type silicon is transferred to or deposited on graphene, and we also observe rectification and photoresponse in the visible range for some of these p-type Schottky junctions. These results are an important step toward the realization of functional graphene adjustable-barrier phototransistors.},
language = {en}
}
@misc{MoralesPlateMarthetal.,
author = {Morales, Carlos and Plate, Paul and Marth, Ludwig and Naumann, Franziska and Kot, Małgorzata and Janowitz, Christoph and Kus, Peter and Z{\"o}llner, Marvin Hartwig and Wenger, Christian and Henkel, Karsten and Flege, Jan Ingo},
title = {Bottom-up design of a supercycle recipe for atomic layer deposition of tunable Indium Gallium Zinc Oxide thin films},
series = {ACS Applied Electronic Materials},
volume = {6},
journal = {ACS Applied Electronic Materials},
number = {8},
publisher = {American Chemical Society (ACS)},
issn = {2637-6113},
doi = {10.1021/acsaelm.4c00730},
pages = {5694 -- 5704},
abstract = {We present a successful bottom-up approach to design a generic plasma-enhanced atomic layer deposition (PEALD) supercycle recipe to grow high-quality indium gallium zinc oxide (IGZO) thin films with tunable composition at a relatively low temperature of 150 °C. In situ real-time ellipsometric characterization in combination with ex situ complementary techniques has been used to optimize the deposition process and quality of the films by identifying and solving growth challenges such as degree of oxidation, nucleation delays, or elemental composition. The developed supercycle approach enables facile control of the target composition by adapting the subcycle ratios within the supercycle process. Compared to other low-temperature deposition techniques resulting in amorphous films, our PEALD-IGZO process at 150 °C results in nearly amorphous, nanocrystalline films. The preparation of IGZO films at low temperature by a supercycle PEALD approach allows controlling the thickness, composition, and electrical properties while preventing thermally induced segregation.},
language = {en}
}
@misc{HayatRatzkeAlvaradoChavarinetal.,
author = {Hayat, Ahsan and Ratzke, Markus and Alvarado Chavarin, Carlos and Z{\"o}llner, Marvin Hartwig and Corley-Wiciak, Agnieszka Anna and Schubert, Markus Andreas and Wenger, Christian and Fischer, Inga Anita},
title = {Structural and morphological properties of CeO2 films deposited by radio frequency magnetron sputtering for back-end-of-line integration},
series = {Thin Solid Films},
volume = {807},
journal = {Thin Solid Films},
issn = {0040-6090},
doi = {10.1016/j.tsf.2024.140547},
pages = {3},
language = {en}
}
@misc{FritscherSinghRizzietal.,
author = {Fritscher, Markus and Singh, Simranjeet and Rizzi, Tommaso and Baroni, Andrea and Reiser, Daniel and Mallah, Maen and Hartmann, David and Bende, Ankit and Kempen, Tim and Uhlmann, Max and Kahmen, Gerhard and Fey, Dietmar and Rana, Vikas and Menzel, Stephan and Reichenbach, Marc and Krstic, Milos and Merchant, Farhad and Wenger, Christian},
title = {A flexible and fast digital twin for RRAM systems applied for training resilient neural networks},
series = {Scientific Reports},
volume = {14},
journal = {Scientific Reports},
number = {1},
publisher = {Springer Science and Business Media LLC},
issn = {2045-2322},
doi = {10.1038/s41598-024-73439-z},
pages = {13},
abstract = {Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the "ideal memristor" which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a "push button" modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).},
language = {en}
}
@misc{LukosiusLukoseDubeyetal.,
author = {Lukosius, Mindaugas and Lukose, Rasuolė and Dubey, P. K. and Raju, A. I. and Capista, Daniele and Lisker, Marco and Mai, A. and Wenger, Christian},
title = {Graphene for photonic applications},
series = {2024 47th MIPRO ICT and Electronics Convention (MIPRO)},
journal = {2024 47th MIPRO ICT and Electronics Convention (MIPRO)},
publisher = {IEEE},
isbn = {979-8-3503-8250-1},
issn = {2623-8764},
doi = {10.1109/MIPRO60963.2024.10569652},
pages = {1614 -- 1618},
abstract = {Integrating graphene into Silicon Complementary Metal-Oxide-Semiconductor (CMOS) technology for photonic applications holds immense promise, but it encounters challenges in establishing large-scale graphene processes. These challenges encompass growth through techniques like Chemical Vapor Deposition (CVD), transfer, encapsulation, and contact formation within a routine 200mm wafer pilot line typically utilized for integrated circuit fabrication. This study is dedicated to exploring various facets of graphene research within a 200 mm pilot line, with a focus on overcoming challenges through the fabrication of proof-of-concept photonic graphene-based devices. The synthesis of graphene targeted epi-Ge(100)/Si(100) substrates, grown within the IHP pilot line, showcasing the potential for high-quality graphene deposition across 200mm wafers. Alternatively, employing different orientations such as (110) has been explored to enhance graphene mobility, achieving a remarkable mobility of 2300 cm 2 /Vs at present. The study systematically investigates graphene quality, thickness, and homogeneity utilizing techniques such as Raman spectroscopy, Atomic Force Microscopy (AFM), and Scanning Electron Microscopy (SEM). Additionally, simulations and fabrication of the graphene ring modulators have been conducted at both the component and device levels, incorporating realistic graphene properties. These results indicate a modulation depth of 1.6 dB/μm and a 3dB bandwidth of 7 GHz, showcasing the potential of graphene-based photonic devices for high-speed communication applications.},
language = {en}
}
@misc{FritscherWengerKrstic,
author = {Fritscher, Markus and Wenger, Christian and Krstic, Milos},
title = {From device to application - integrating RRAM Accelerator Blocks into large AI systems},
series = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
journal = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
publisher = {IEEE},
isbn = {979-8-3503-5411-9},
issn = {2159-3477},
doi = {10.1109/ISVLSI61997.2024.00111},
pages = {592 -- 592},
abstract = {This work provides an introduction to design methodologies for RRAM-based systems. We illustrate the impact of device variation on the performance of neural networks and propose a circuit-level integration approach for RRAM-based compute blocks. Moreover, we demonstrate a possible architectural integration by incorporating RRAM-based VMM blocks fabricated in a 130 nm CMOS process into a RISC-V.},
language = {en}
}
@misc{FritscherUhlmannOstrovskyyetal.,
author = {Fritscher, Markus and Uhlmann, Max and Ostrovskyy, Philip and Reiser, Daniel and Chen, Junchao and Schubert, Andreas and Schulze, Carsten and Kahmen, Gerhard and Fey, Dietmar and Reichenbach, Marc and Krstic, Milos and Wenger, Christian},
title = {Area-efficient digital design using RRAM-CMOS standard cells},
series = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
volume = {18},
journal = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
publisher = {IEEE},
isbn = {979-8-3503-5411-9},
issn = {2159-3477},
doi = {10.1109/ISVLSI61997.2024.00026},
pages = {81 -- 87},
abstract = {Extending the scalability of digital integrated circuits through novel device concepts is an attractive option. Among these concepts, resistive random access memory (RRAM) devices allow fast and nonvolatile operation. However, building large memristive systems is still challenging since large analog circuits have to be designed and integrated. In this paper, we propose a novel solution - the implementation of digital standard cells by the means of RRAM devices. While this methodology is universal, with applications ranging from few-device-circuits to large macroblocks, we demonstrate it for a 2T2R-cell. The benefits of using RRAM devices are demonstrated by implementing a NAND standard cell merely consuming the area of two transistors. This cell is about 25 \% smaller than the equivalent CMOS NAND in the same technology. We use these cells to implement a half adder, beating the area of the equivalent CMOS implementation using more sophisticates gates by 15 \%. Lastly, we fully integrate this novel standard cell into a digital standard cell library and perform a synthesis and layout of a RISC-V CPU core.},
language = {en}
}
@misc{VinuesaGarciaDuenasetal.,
author = {Vinuesa, Guillermo and Garcia, Hector and Duenas, Salvador and Castan, Helena and I{\~n}iguez de la Torre, Ignacio and Gonzalez, Tomas and Dorai Swamy Reddy, Keerthi and Uhlmann, Max and Wenger, Christian and Perez, Eduardo},
title = {Effect of the temperature on the performance and dynamic behavior of HfO2-Based Rram Devices},
series = {ECS Meeting Abstracts},
volume = {MA2024-01},
journal = {ECS Meeting Abstracts},
number = {21},
publisher = {The Electrochemical Society},
issn = {2151-2043},
doi = {10.1149/MA2024-01211297mtgabs},
pages = {1297 -- 1297},
abstract = {Over the past decades, the demand for semiconductor memory devices has been steadily increasing, and is currently experiencing an unprecedented boost due to the development and expansion of artificial intelligence. Among emerging high-density non-volatile memories, resistive random-access memory (RRAM) is one of the best recourses for all kind of applications, such as neuromorphic computing or hardware security [1]. Although many materials have been evaluated for RRAM development, some of them with excellent results, HfO2 is one of the established materials in CMOS domain due to its compatibility with standard materials and processes [2]. The main goal of this work is to study the switching capability and stability of HfO2-based RRAMs, as well as to explore their ability in the field of analogue applications, by analyzing the evolution of the resistance states that allow multilevel control. Indeed, analogue operation is a key point for achieving electronic neural synapses in neuromorphic systems, with synaptic weight information encoded in the different resistance states. This research has been carried out over a wide temperature range, between 40 and 340 K, as we are interested in testing the extent to which performance is maintained or modified, with a view to designing neuromorphic circuits that are also suitable in the low-temperature realm. We aim to prove that these simple, fast, high integration density structures can also be used in circuits designed for specific applications, such as aerospace systems. The RRAM devices studied in this work are TiN/Ti/8 nm-HfO2/TiN metal-insulator-metal (MIM) capacitors. Dielectric layers were atomic layer deposited (ALD). It has been demonstrated that the Ti coat in the top electrode acts as a scavenger that absorbs oxygen atoms from the HfO2 layer, and facilitates the creation of conductive filaments of oxygen vacancies [3]. In fact, the oxygen reservoir capability of Ti is well known, as it is able to attract and release oxygen atoms from or to the HfO2 layer during the RRAM operation [4]. The clustering of vacancies extends through the entire thickness of the oxide and, after an electroformig step, it joins the upper and lower electrodes and the device reaches the low resistance state (LRS). By applying adequate electrical signals, the filaments can be partially dissolved, which brings the device into the high-resistance state (HRS), with lower current values. The set process brings the device to the LRS state, while the reset one brings it to the HRS. The dependence of electrical conductivity on external applied electrical excitation allows triggering the device between the both states in a non-volatile manner [5]. The experimental equipment used consisted of a Keithley 4200-SCS semiconductor parameter analyzer and a Lake Shore cryogenic probe station. Fig.1 shows current-voltage cycles measured at different temperatures; the averages values at each temperature, both in logarithmic and linear scale, are also shown. The functional window increases as temperature decreases. The evolutions of set and reset voltage values with temperature are depicted in Fig.2, whereas the current values (measured at 0.1 V) corresponding to the LRS and HRS can be seen in Fig.3. LRS resistance decreases as temperature increases, in agreement with semiconductor behaviour, probably due to a hopping conduction mechanism. Both set and reset voltages decrease as temperature increases; the reset process is smoother at high temperatures. The reduction in reset voltage variability as temperature increases is very notable. Finally, Fig. 4 shows a picture of the transient behaviour; in the right panel of the same figure, the amplitudes of the current transients in the reset state have been included in the external loop. To sum up, the resistive switching phenomena is studied in a wide temperature range. The LRS shows semiconducting behavior with temperature, most likely related to a hopping conduction mechanism. Switching voltages decrease as temperature increases, with a notable reduction in reset voltage variability. An excellent control of intermediate resistance state is shown through current transients at several voltages in the reset process. REFERENCES [1] M. Asif et al., Materials Today Electronics 1, 100004 (2022). [2] S. Slesazeck et al., Nanotechnology 30, 352003 (2019). [3] Z. Fang et al., IEEE Electron Device Letters 35, 9, 912-914 (2014). [4] H. Y. Lee et al., IEEE Electron Device Letters 31, 1, 44-46 (2010). [5] D. J. Wouters et al., Proceedings of the IEEE 103, 8, 1274-1288 (2015). Figure 1},
language = {en}
}
@misc{WenBaroniPerezetal.,
author = {Wen, Jianan and Baroni, Andrea and Perez, Eduardo and Uhlmann, Max and Fritscher, Markus and KrishneGowda, Karthik and Ulbricht, Markus and Wenger, Christian and Krstic, Milos},
title = {Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator},
series = {2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
journal = {2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
publisher = {IEEE},
isbn = {978-3-9819263-8-5},
issn = {1558-1101},
doi = {10.23919/DATE58400.2024.10546709},
pages = {1 -- 6},
abstract = {The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 \% and 18 \%, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83\% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero.},
language = {en}
}
@misc{MaldonadoBaroniAldanaetal.,
author = {Maldonado, David and Baroni, Andrea and Aldana, Samuel and Dorai Swamy Reddy, Keerthi and Pechmann, Stefan and Wenger, Christian and Rold{\´a}n, Juan Bautista and P{\´e}rez, Eduardo},
title = {Kinetic Monte Carlo simulation analysis of the conductance drift in Multilevel HfO2-based RRAM devices},
series = {Nanoscale},
volume = {16},
journal = {Nanoscale},
number = {40},
publisher = {Royal Society of Chemistry (RSC)},
issn = {2040-3364},
doi = {10.1039/d4nr02975e},
pages = {19021 -- 19033},
abstract = {The drift characteristics of valence change memory (VCM) devices have been analyzed through both experimental analysis and 3D kinetic Monte Carlo (kMC) simulations.},
language = {en}
}
@misc{UhlmannRizziWenetal.,
author = {Uhlmann, Max and Rizzi, Tommaso and Wen, Jianan and P{\´e}rez-Bosch Quesada, Emilio and Al Beattie, Bakr and Ochs, Karlheinz and P{\´e}rez, Eduardo and Ostrovskyy, Philip and Carta, Corrado and Wenger, Christian and Kahmen, Gerhard},
title = {LUT-based RRAM model for neural accelerator circuit simulation},
series = {Proceedings of the 18th ACM International Symposium on Nanoscale Architectures},
journal = {Proceedings of the 18th ACM International Symposium on Nanoscale Architectures},
publisher = {ACM},
address = {New York, NY, USA},
doi = {10.1145/3611315.3633273},
pages = {1 -- 6},
abstract = {Neural hardware accelerators have been proven to be energy-efficient when used to solve tasks which can be mapped into an artificial neural network (ANN) structure. Resistive random-access memories (RRAMs) are currently under investigation together with several different memristive devices as promising technologies to build such accelerators combined together with complementary metal-oxide semiconductor (CMOS)-technologies in integrated circuits (ICs). While many research groups are actively developing sophisticated physical-based representations to better understand the underlying phenomena characterizing these devices, not much work has been dedicated to exploit the trade-off between simulation time and accuracy in the definition of low computational demanding models suitable to be used at many abstraction layers. Indeed, the design of complex mixed-signal systems as a neural hardware accelerators requires frequent interaction between the application- and the circuit-level that can be enabled only with the support of accurate and fast-simulating devices' models. In this work, we propose a solution to fill the aforementioned gap with a lookup table (LUT)-based Verilog-A model of IHP's 1-transistor-1-RRAM (1T1R) cell. In addition, the implementation challenges of conveying the communication between the abstract ANN simulation and the circuital analysis are tackled with a design flow for resistive neural hardware accelerators that features a custom Python wrapper. As a demonstration of the proposed design flow and 1T1R model, an ANN for the MNIST handwritten digit recognition task is assessed with the last layer verified in circuit simulation. The obtained recognition confidence intervals show a considerable discrepancy between the purely application-level PyTorch simulation and the proposed design flow which spans across the abstraction layers down to the circuital analysis.},
language = {en}
}
@misc{StrobelAlvaradoChavarinVoelkeletal.,
author = {Strobel, Carsten and Alvarado Chavarin, Carlos and V{\"o}lkel, Sandra and Jahn, Andreas and Hiess, Andre and Knaut, Martin and Albert, Matthias and Wenger, Christian and Steinke, Olaff and Stephan, Ulf and R{\"o}hlecke, S{\"o}ren and Mikolajick, Thomas},
title = {Enhanced Electrical Properties of Optimized Vertical Graphene-Base Hot Electron Transistors},
series = {ACS Applied Electronic Materials},
volume = {5},
journal = {ACS Applied Electronic Materials},
number = {3},
issn = {2637-6113},
doi = {10.1021/acsaelm.2c01725},
pages = {1670 -- 1675},
abstract = {The arrival of high-mobility two-dimensional materials like graphene leads to the renaissance of former vertical semiconductor-metal-semiconductor (SMS) hot electron transistors. Because of the monolayer thickness of graphene, improved SMS transistors with a semimetallic graphene-base electrode are now feasible for high-frequency applications. In this study we report about a device that consists of amorphous silicon, graphene, and crystalline silicon. For the first time, this device is fabricated by a four-mask lithography process which leads to significant improvements in the device performance. A strongly increased common-emitter current gain of 2\% could be achieved while the on-off ratio improved to 1.6 × 105, which is already higher than predicted theoretically. This could be mainly attributed to better interface characteristics and decreased lateral dimensions of the devices. A cutoff frequency of approximately 26 MHz could be forecasted based on the DC measurements of the device.},
language = {en}
}
@misc{KloesBischoffLeiseetal.,
author = {Kloes, Alexander and Bischoff, Carl and Leise, Jakob and Perez-Bosch Quesada, Emilio and Wenger, Christian and P{\´e}rez, Eduardo},
title = {Stochastic switching of memristors and consideration in circuit simulation},
series = {Solid State Electronics},
volume = {201},
journal = {Solid State Electronics},
issn = {0038-1101},
doi = {10.1016/j.sse.2023.108606},
abstract = {We explore the stochastic switching of oxide-based memristive devices by using the Stanford model for circuit simulation. From measurements, the device-to-device (D2D) and cycle-to-cycle (C2C) statistical variation is extracted. In the low-resistive state (LRS) dispersion by D2D variability is dominant. In the high-resistive state (HRS) C2C dispersion becomes the main source of fluctuation. A statistical procedure for the extraction of parameters of the compact model is presented. Thereby, in a circuit simulation the typical D2D and C2C fluctuations of the current-voltage (I-V) characteristics can be emulated by extracting statistical parameters of key model parameters. The statistical distributions of the parameters are used in a Monte Carlo simulation to reproduce the I-V D2D and C2C dispersions which show a good agreement to the measured curves. The results allow the simulation of the on/off current variation for the design of memory cells or can be used to emulate the synaptic behavior of these devices in artificial neural networks realized by a crossbar array of memristors.},
language = {en}
}
@misc{PerezBoschQuesadaMahadevaiahRizzietal.,
author = {Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Rizzi, Tommaso and Wen, Jianan and Ulbricht, Markus and Krstic, Milos and Wenger, Christian and P{\´e}rez, Eduardo},
title = {Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing},
series = {IEEE Transactions on Electron Devices},
volume = {70},
journal = {IEEE Transactions on Electron Devices},
number = {4},
issn = {0018-9383},
doi = {10.1109/TED.2023.3244509},
pages = {2009 -- 2014},
abstract = {Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of 8x8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices' nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems.},
language = {en}
}
@misc{AkhtarDabrowskiLukoseetal.,
author = {Akhtar, Fatima and Dabrowski, Jaroslaw and Lukose, Rasuole and Wenger, Christian and Lukosius, Mindaugas},
title = {Chemical Vapor Deposition Growth of Graphene on 200 mm Ge (110)/Si Wafers and Ab Initio Analysis of Differences in Growth Mechanisms on Ge (110) and Ge (001)},
series = {ACS Applied Materials \& Interfaces},
volume = {15},
journal = {ACS Applied Materials \& Interfaces},
number = {30},
issn = {1944-8244},
doi = {10.1021/acsami.3c05860},
pages = {36966 -- 36974},
abstract = {For the fabrication of modern graphene devices, uniform growth of high-quality monolayer graphene on wafer scale is important. This work reports on the growth of large-scale graphene on semiconducting 8 inch Ge(110)/Si wafers by chemical vapor deposition and a DFT analysis of the growth process. Good graphene quality is indicated by the small FWHM (32 cm-1) of the Raman 2D band, low intensity ratio of the Raman D and G bands (0.06), and homogeneous SEM images and is confirmed by Hall measurements: high mobility (2700 cm2/Vs) and low sheet resistance (800 Ω/sq). In contrast to Ge(001), Ge(110) does not undergo faceting during the growth. We argue that Ge(001) roughens as a result of vacancy accumulation at pinned steps, easy motion of bonded graphene edges across (107) facets, and low energy cost to expand Ge area by surface vicinals, but on Ge(110), these mechanisms do not work due to different surface geometries and complex reconstruction.},
language = {en}
}
@misc{RizziBaroniGlukhovetal.,
author = {Rizzi, Tommaso and Baroni, Andrea and Glukhov, Artem and Bertozzi, Davide and Wenger, Christian and Ielmini, Daniele and Zambelli, Cristian},
title = {Process-Voltage-Temperature Variations Assessment in Energy-Aware Resistive RAM-Based FPGAs},
series = {IEEE Transactions on Device and Materials Reliability},
volume = {23},
journal = {IEEE Transactions on Device and Materials Reliability},
number = {3},
issn = {1530-4388},
doi = {10.1109/TDMR.2023.3259015},
pages = {328 -- 336},
abstract = {Resistive Random Access Memory (RRAM) technology holds promises to improve the Field Programmable Gate Array (FPGA) performance, reduce the area footprint, and dramatically lower run-time energy requirements compared to the state-of-the-art CMOS-based products. However, the integration of RRAM in FPGAs is hindered by the high programming power consumption and by non-ideal behaviors of the device due to its stochastic nature that may overshadow the benefits in normal operation mode. To cope with these challenges, optimized programming strategies have to be investigated. In this work, we explore the impact that different procedures to set the device have on the run-time performance. Process, voltage, and temperature (PVT) variations as well as time-dependent drift effect of the RRAM device are considered in the assessment of 4T1R MUX designs characteristics. The comparison with tradition CMOS implementations reveals how the choice of the target resistive state and the programming algorithm are key design aspects to reduce the run-time delay and energy metrics, while at the same time improving the robustness against the different sources of variations.},
language = {en}
}
@misc{UhlmannPerezBoschQuesadaFritscheretal.,
author = {Uhlmann, Max and P{\´e}rez-Bosch Quesada, Emilio and Fritscher, Markus and P{\´e}rez, Eduardo and Schubert, Markus Andreas and Reichenbach, Marc and Ostrovskyy, Philip and Wenger, Christian and Kahmen, Gerhard},
title = {One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing},
series = {21st IEEE Interregional NEWCAS Conference (NEWCAS)},
journal = {21st IEEE Interregional NEWCAS Conference (NEWCAS)},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
isbn = {979-8-3503-0024-6},
issn = {2474-9672},
doi = {10.1109/NEWCAS57931.2023.10198073},
pages = {5},
abstract = {The use of resistive random-access memory (RRAM) for in-memory computing (IMC) architectures has significantly improved the energy-efficiency of artificial neural networks (ANN) over the past years. Current RRAM-technologies are physically limited to a defined unambiguously distinguishable number of stable states and a maximum resistive value and are compatible with present complementary metal-oxide semiconductor (CMOS)-technologies. In this work, we improved the accuracy of current ANN models by using increased weight resolutions of memristive devices, combining two or more in-series RRAM cells, integrated in the back end of line (BEOL) of the CMOS process. Based on system level simulations, 1T2R devices were fabricated in IHP's 130nm SiGe:BiCMOS technology node, demonstrating an increased number of states. We achieved an increase in weight resolution from 3 bit in ITIR cells to 6.5 bit in our 1T2R cell. The experimental data of 1T2R devices gives indications for the performance and energy-efficiency improvement in ITNR arrays for ANN applications.},
language = {en}
}
@misc{StrobelAlvaradoChavarinWengeretal.,
author = {Strobel, Carsten and Alvarado Chavarin, Carlos and Wenger, Christian and Albert, Matthias and Mikolajick, Thomas},
title = {Vertical Graphene-Based Transistors for Power Electronics, Optoelectronics and Radio-Frequency Applications},
series = {IEEE Nanotechnology Materials and Devices Conference (NMDC), Paestum, Italy, 22-25 October 2023},
journal = {IEEE Nanotechnology Materials and Devices Conference (NMDC), Paestum, Italy, 22-25 October 2023},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
isbn = {979-8-3503-3546-0},
issn = {2473-0718},
doi = {10.1109/NMDC57951.2023.10344102},
pages = {196 -- 201},
abstract = {The combination of two-dimensional materials, such as graphene, with established thin films offers great opportunities for enabling next-generation vertical transistors for various applications. This paper gives a brief overview about different vertical transistor concepts using twodimensional materials proposed so far, e.g. the hot electron transistor and the Barristor. With the arrival of twodimensional materials, the hot electron transistor also experienced a revival with predicted cut-off frequencies in the THz range. The Barristor overcomes the weak current saturation of lateral graphene field-effect transistors and high on-off ratios up to 107 were demonstrated, which are suitable parameters for logic applications. By combining a semiconductor-graphene-semiconductor design of the simplest hot electron transistor with the Barristor operating principle a new device, called graphene adjustable-barriers transistor, can be realized. This new device concept provides the potential for RF, power electronics, and optoelectronic applications.},
language = {en}
}
@misc{MoralesMahmoodinezhadTschammeretal.,
author = {Morales, Carlos and Mahmoodinezhad, Ali and Tschammer, Rudi and Kosto, Yuliia and Alvarado Chavarin, Carlos and Schubert, Markus Andreas and Wenger, Christian and Henkel, Karsten and Flege, Jan Ingo},
title = {Combination of Multiple Operando and In-Situ Characterization Techniques in a Single Cluster System for Atomic Layer Deposition: Unraveling the Early Stages of Growth of Ultrathin Al2O3 Films on Metallic Ti Substrates},
series = {Inorganics},
volume = {11},
journal = {Inorganics},
number = {12},
issn = {2304-6740},
doi = {10.3390/inorganics11120477},
abstract = {This work presents a new ultra-high vacuum cluster tool to perform systematic studies of the early growth stages of atomic layer deposited (ALD) ultrathin films following a surface science approach. By combining operando (spectroscopic ellipsometry and quadrupole mass spectrometry) and in situ (X-ray photoelectron spectroscopy) characterization techniques, the cluster allows us to follow the evolution of substrate, film, and reaction intermediates as a function of the total number of ALD cycles, as well as perform a constant diagnosis and evaluation of the ALD process, detecting possible malfunctions that could affect the growth, reproducibility, and conclusions derived from data analysis. The homemade ALD reactor allows the use of multiple precursors and oxidants and its operation under pump and flow-type modes. To illustrate our experimental approach, we revisit the well-known thermal ALD growth of Al2O3 using trimethylaluminum and water. We deeply discuss the role of the metallic Ti thin film substrate at room temperature and 200 °C, highlighting the differences between the heterodeposition (<10 cycles) and the homodeposition (>10 cycles) growth regimes at both conditions. This surface science approach will benefit our understanding of the ALD process, paving the way toward more efficient and controllable manufacturing processes.},
language = {en}
}
@misc{CapistaLukoseMajnoonetal.,
author = {Capista, Daniele and Lukose, Rasuole and Majnoon, Farnaz and Lisker, Marco and Wenger, Christian and Lukosius, Mindaugas},
title = {Study on the metal -graphene contact resistance achieved with one -dimensional contact architecture},
series = {IEEE Nanotechnology Materials and Devices Conference (NMDC 2023), Paestum, Italy, 22-25 October 2023},
journal = {IEEE Nanotechnology Materials and Devices Conference (NMDC 2023), Paestum, Italy, 22-25 October 2023},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
isbn = {979-8-3503-3546-0},
doi = {10.1109/NMDC57951.2023.10343775},
pages = {118 -- 119},
abstract = {Graphene has always been considered as one of the materials with the greatest potential for the realization of improved microelectronic and photonic devices. But to actually reach its full potential in Si CMOS technology, graphene -based devices need to overcome different challenges. They do not only need to have better performances than standard devices, but they also need to be compatible with the production of standard Si based devices. To address the first challenge the main route requires the optimization of the contact resistance, that highly reduces the devices performance, while the second challenges requires the integration of graphene inside the standard production lines used for microelectronic. In this work we used an 8" wafer pilot -line to realize our devices and we studied the behavior of the contact resistance between metal and graphene obtained by one -dimensional contact architecture between the two materials. The contact resistance has been measured by means of Transmission Line Method (TLM) with several contact patterning.},
language = {en}
}
@misc{LukosiusLukoseLiskeretal.,
author = {Lukosius, Mindaugas and Lukose, Rasuolė and Lisker, Marco and Dubey, P. K. and Raju, A. I. and Capista, Daniele and Majnoon, Farnaz and Mai, A. and Wenger, Christian},
title = {Developments of Graphene devices in 200 mm CMOS pilot line},
series = {Proc. Nanotechnology Materials and Devices Conference (NMDC 2023),Paestum, Italy, 22-25 October 2023},
journal = {Proc. Nanotechnology Materials and Devices Conference (NMDC 2023),Paestum, Italy, 22-25 October 2023},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
isbn = {979-8-3503-3546-0},
doi = {10.1109/NMDC57951.2023.10343569},
pages = {505 -- 506},
abstract = {Due to the unique electronic band structure, graphene has opened great potential to extend the functionality of a large variety of devices. Despite the significant progress in the fabrication of various graphene based microelectronic devices, the integration of graphene devices still lack the stability and compatibility with Si-technology processes. Therefore, the investigation and preparation of graphene devices in conditions resembling as close as possible the Si technology environment is of highest importance. This study aims to explore various aspects of graphene research on a 200mm pilot line, with a focus on simulations and fabrication of graphene modulator. To be more precise, it includes design and fabrication of the layouts, necessary mask sets, creation of the flows, fabrication, and measurements of the Gr modulators on 200 mm wafers.},
language = {en}
}
@misc{MaldonadoCantudoPerezetal.,
author = {Maldonado, David and Cantudo, Antonio and P{\´e}rez, Eduardo and Romero-Zaliz, Rocio and Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista},
title = {TiN/Ti/HfO2/TiN Memristive Devices for Neuromorphic Computing: From Synaptic Plasticity to Stochastic Resonance},
series = {Frontiers in Neuroscience},
volume = {17},
journal = {Frontiers in Neuroscience},
issn = {1662-4548},
doi = {10.3389/fnins.2023.1271956},
abstract = {We characterize TiN/Ti/HfO2/TiN memristive devices for neuromorphic computing. We analyze different features that allow the devices to mimic biological synapses and present the models to reproduce analytically some of the data measured. In particular, we have measured the spike timing dependent plasticity behavior in our devices and later on we have modeled it. The spike timing dependent plasticity model was implemented as the learning rule of a spiking neural network that was trained to recognize the MNIST dataset. Variability is implemented and its influence on the network recognition accuracy is considered accounting for the number of neurons in the network and the number of training epochs. Finally, stochastic resonance is studied as another synaptic feature.It is shown that this effect is important and greatly depends on the noise statistical characteristics.},
language = {en}
}
@misc{PerezBoschQuesadaRizziGuptaetal.,
author = {Perez-Bosch Quesada, Emilio and Rizzi, Tommaso and Gupta, Aditya and Mahadevaiah, Mamathamba Kalishettyhalli and Schubert, Andreas and Pechmann, Stefan and Jia, Ruolan and Uhlmann, Max and Hagelauer, Amelie and Wenger, Christian and P{\´e}rez, Eduardo},
title = {Multi-Level Programming on Radiation-Hard 1T1R Memristive Devices for In-Memory Computing},
series = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023},
journal = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
isbn = {979-8-3503-0240-0},
doi = {10.1109/CDE58627.2023.10339525},
pages = {4},
abstract = {This work presents a quasi-static electrical characterization of 1-transistor-1-resistor memristive structures designed following hardness-by-design techniques integrated in the CMOS fabrication process to assure multi-level capabilities in harsh radiation environments. Modulating the gate voltage of the enclosed layout transistor connected in series with the memristive device, it was possible to achieve excellent switching capabilities from a single high resistance state to a total of eight different low resistance states (more than 3 bits). Thus, the fabricated devices are suitable for their integration in larger in-memory computing systems and in multi-level memory applications. Index Terms—radiation-hard, hardness-by-design, memristive devices, Enclosed Layout Transistor, in-memory computing},
language = {en}
}
@misc{PerezMaldonadoMahadevaiahetal.,
author = {P{\´e}rez, Eduardo and Maldonado, David and Mahadevaiah, Mamathamba Kalishettyhalli and Perez-Bosch Quesada, Emilio and Cantudo, Antonio and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista},
title = {A comparison of resistive switching parameters for memristive devices with HfO2 monolayers and Al2O3/HfO2 bilayers at the wafer scale},
series = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023},
journal = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
isbn = {979-8-3503-0240-0},
doi = {10.1109/CDE58627.2023.10339417},
pages = {5},
abstract = {Memristive devices integrated in 200 mm wafers manufactured in 130 nm CMOS technology with two different dielectrics, namely, a HfO2 monolayer and an Al2O3/HfO2 bilayer, have been measured. The cycle-to-cycle (C2C) and device-todevice (D2D) variability have been analyzed at the wafer scale using different numerical methods to extract the set (Vset) and reset (Vreset) voltages. Some interesting differences between both technologies were found in terms of switching characteristics},
language = {en}
}
@misc{ReiserReichenbachRizzietal.,
author = {Reiser, Daniel and Reichenbach, Marc and Rizzi, Tommaso and Baroni, Andrea and Fritscher, Markus and Wenger, Christian and Zambelli, Cristian and Bertozzi, Davide},
title = {Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations},
series = {21st IEEE Interregional NEWCAS Conference (NEWCAS), 26-28 June 2023, Edinburgh, United Kingdom},
journal = {21st IEEE Interregional NEWCAS Conference (NEWCAS), 26-28 June 2023, Edinburgh, United Kingdom},
publisher = {IEEE},
address = {Piscataway, NJ},
isbn = {979-8-3503-0024-6},
doi = {10.1109/NEWCAS57931.2023},
abstract = {In-memory computing with resistive-switching random access memory (RRAM) crossbar arrays has the potential to overcome the major bottlenecks faced by digital hardware for data-heavy workloads such as deep learning. However, RRAM devices are subject to several non-idealities that result in significant inference accuracy drops compared with software baseline accuracy. A critical one is related to the drift of the conductance states appearing immediately at the end of program and verify algorithms that are mandatory for accurate multi-level conductance operation. The support of drift models in state-of-the-art simulation tools of memristive computationin-memory is currently only in the early stage, since they overlook key device- and array-level parameters affecting drift resilience such as the programming algorithm of RRAM cells, the choice of target conductance states and the weight-toconductance mapping scheme. The goal of this paper is to fully expose these parameters to RRAM crossbar designers as a multi-dimensional optimization space of drift resilience. For this purpose, a simulation framework is developed, which comes with the suitable abstractions to propagate the effects of those RRAM crossbar configuration parameters to their ultimate implications over inference performance stability.},
language = {en}
}
@misc{FranckDabrowskiSchubertetal.,
author = {Franck, Max and Dabrowski, Jarek and Schubert, Markus Andreas and Vignaud, Dominique and Achehboune, Mohamed and Colomer, Jean-Fran{\c{c}}ois and Henrard, Luc and Wenger, Christian and Lukosius, Mindaugas},
title = {Investigating Impacts of Local Pressure and Temperature on CVD Growth of Hexagonal Boron Nitride on Ge(001)/Si},
series = {Advanced Materials Interfaces},
volume = {12},
journal = {Advanced Materials Interfaces},
number = {1},
publisher = {Wiley},
issn = {2196-7350},
doi = {10.1002/admi.202400467},
pages = {9},
abstract = {AbstractThe chemical vapor deposition (CVD) growth of hexagonal boron nitride (hBN) on Ge substrates is a promising pathway to high-quality hBN thin films without metal contaminations for microelectronic applications, but the effect of CVD process parameters on the hBN properties is not well understood yet. The influence of local changes in pressure and temperature due to different reactor configurations on the structure and quality of hBN films grown on Ge(001)/Si is studied. Injection of the borazine precursor close to the sample surface results in an inhomogeneous film thickness, attributed to an inhomogeneous pressure distribution at the surface, as shown by computational fluid dynamics simulations. The additional formation of nanocrystalline islands is attributed to unfavorable gas phase reactions due to the radiative heating of the injector. Both issues are mitigated by increasing the injector-sample distance, leading to an 86\% reduction in pressure variability on the sample surface and a 200 °C reduction in precursor temperature. The resulting hBN films exhibit no nanocrystalline islands, improved thickness homogeneity, and high crystalline quality (Raman FWHM = 23 cm-1). This is competitive with hBN films grown on other non-metal substrates but achieved at lower temperature and with a low thickness of only a few nanometers.},
language = {en}
}
@misc{WenVargasZhuetal.,
author = {Wen, Jianan and Vargas, Fabian Luis and Zhu, Fukun and Reiser, Daniel and Baroni, Andrea and Fritscher, Markus and Perez, Eduardo and Reichenbach, Marc and Wenger, Christian and Krstic, Milos},
title = {RRAMulator : an efficient FPGA-based emulator for RRAM crossbar with device variability and energy consumption evaluation},
series = {Microelectronics Reliability},
volume = {168},
journal = {Microelectronics Reliability},
publisher = {Elsevier BV},
address = {Amsterdam},
issn = {0026-2714},
doi = {10.1016/j.microrel.2025.115630},
pages = {1 -- 10},
abstract = {The in-memory computing (IMC) systems based on emerging technologies have gained significant attention due to their potential to enhance performance and energy efficiency by minimizing data movement between memory and processing unit, which is especially beneficial for data-intensive applications. Designing and evaluating systems utilizing emerging memory technologies, such as resistive RAM (RRAM), poses considerable challenges due to the limited support from electronics design automation (EDA) tools for rapid development and design space exploration. Additionally, incorporating technology-dependent variability into system-level simulations is critical to accurately assess the impact on system reliability and performance. To bridge this gap, we propose RRAMulator, a field-programmable gate array (FPGA) based hardware emulator for RRAM crossbar array. To avoid the complex device models capturing the nonlinear current-voltage (IV) relationships that degrade emulation speed and increase hardware utilization, we propose a device and variability modeling approach based on device measurements. We deploy look-up tables (LUTs) for device modeling and use the multivariate kernel density estimation (KDE) method to augment existing data, extending data variety and avoiding repetitive data usage. The proposed emulator achieves cycle-accurate, real-time emulations and provides information such as latency and energy consumption for matrix mapping and vector-matrix multiplications (VMMs). Experimental results show a significant reduction in emulation time compared to conventional behavioral simulations. Additionally, an RRAM-based discrete Fourier transform (DFT) accelerator is analyzed as a case study featuring a range of in-depth system assessments.},
language = {en}
}
@misc{SpetzlerFritscherParketal.,
author = {Spetzler, Benjamin and Fritscher, Markus and Park, Seongae and Kim, Nayoun and Wenger, Christian and Ziegler, Martin},
title = {AI-driven model for optimized pulse programming of memristive devices},
series = {APL Machine Learning},
volume = {3},
journal = {APL Machine Learning},
number = {2},
publisher = {AIP Publishing},
issn = {2770-9019},
doi = {10.1063/5.0251113},
pages = {1 -- 7},
abstract = {Next-generation artificial intelligence (AI) hardware based on memristive devices offers a promising approach to reducing the increasingly large energy consumption of AI applications. However, programming memristive AI hardware to achieve a desired synaptic weight configuration remains challenging because it requires accurate and energy-efficient algorithms for selecting the optimal weight-update pulses. Here, we present a computationally efficient AI model for predicting the weight update of memristive devices and guiding device programming. The synaptic weight-update behavior of bilayer HfO2/TiO2 memristive devices is characterized over a range of pulse parameters to provide experimental data for the AI model. Three different artificial neural network (ANN) configurations are trained and evaluated regarding the amount of training data required for accurate predictions and the computational costs. Finally, we apply the model to an antipulse weight-update process to demonstrate its performance. The results show that accurate and computationally inexpensive predictions are possible with comparatively few datasets and small ANNs. The normalized weight-update processes are predicted with accuracies comparable with larger model architectures but require only 896 floating point operations and 8.33 nJ per inference. This makes the model a promising candidate for integration into AI-driven device controllers as a precise and energy-efficient solution for memristive device programming.},
language = {en}
}
@misc{FritscherUhlmannOstrovskyyetal.,
author = {Fritscher, Markus and Uhlmann, Max and Ostrovskyy, Philip and Reiser, Daniel and Chen, Junchao and Wen, Jianan and Schulze, Carsten and Kahmen, Gerhard and Fey, Dietmar and Reichenbach, Marc and Krstic, Milos and Wenger, Christian},
title = {RISC-V CPU design using RRAM-CMOS standard cells},
series = {IEEE transactions on very large scale integration (VLSI) systems},
journal = {IEEE transactions on very large scale integration (VLSI) systems},
editor = {Wenger, Christian},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
address = {New York},
issn = {1063-8210},
doi = {10.1109/TVLSI.2025.3554476},
pages = {1 -- 9},
abstract = {The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely, creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks, we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors, this enables us to construct a nand standard cell, which merely consumes the area of two transistors. This leads to a 25\% area reduction compared to an equivalent CMOS nand gate. We illustrate achievable area savings with a half-adder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7\% smaller area than the equivalent design using standard CMOS gates.},
language = {en}
}
@misc{StrobelChavarinKnautetal.,
author = {Strobel, Carsten and Chavarin, Carlos A. and Knaut, Martin and Wenger, Christian and Heinzig, Andr{\´e} and Mikolajick, Thomas},
title = {Demonstration of a graphene adjustable-barriers phototransistor with tunable ultra-high responsivity},
series = {Advanced Optical Materials},
journal = {Advanced Optical Materials},
publisher = {Wiley-VCH GmbH},
address = {Weinheim},
issn = {2195-1071},
doi = {10.1002/adom.202500344},
pages = {1 -- 9},
abstract = {The development of high-speed dual-band photodetectors with high responsivity is important for several applications such as optical communication, biomedical imaging or spectroscopy. In this work, a phototransistor with ultra-high responsivity is demonstrated, which potentially also allows for very high bandwidths. The device is called graphene adjustable-barriers phototransistor and is potentially capable for dual-band detection in the visible-infrared (VIS-IR) range. A material combination of intrinsic hydrogenated amorphous silicon, graphene, and n-type germanium (n-Ge) is used for the demonstrator. The device operation is based on the light induced modulation of the graphene Fermi energy level and Schottky barrier heights. For the first time, the functional mechanism of the device is successfully demonstrated in the VIS range with responsivities exceeding 107 A/W at a gate voltage of 20V. The bandwidth of the device is 1.2 kHz and is so far limited by the defective gate material hydrogenated amorphous silicon and relaxed feature sizes of the demonstrator. These results are an important step toward a new generation of high-responsivity high-speed photo detection devices.},
language = {en}
}
@misc{MoralesGertigKotetal.,
author = {Morales, Carlos and Gertig, Max and Kot, Małgorzata and Alvarado, Carlos and Schubert, Markus Andreas and Zoellner, Marvin Hartwig and Wenger, Christian and Henkel, Karsten and Flege, Jan Ingo},
title = {In situ X-ray photoelectron spectroscopy study of atomic layer deposited cerium oxide on SiO₂ : substrate influence on the reaction mechanism during the early stages of growth},
series = {Advanced materials interfaces},
volume = {12},
journal = {Advanced materials interfaces},
number = {5},
publisher = {Wiley},
address = {Weinheim},
issn = {2196-7350},
doi = {10.1002/admi.202400537},
pages = {1 -- 13},
abstract = {Thermal atomic layer deposition (ALD) of cerium oxide using commercial Ce(thd)4 precursor and O3 on SiO2 substrates is studied employing in-situ X-ray photoelectron spectroscopy (XPS). The system presents a complex growth behavior determined by the change in the reaction mechanism when the precursor interacts with the substrate or the cerium oxide surface. During the first growth stage, non-ALD side reactions promoted by the substrate affect the growth per cycle, the amount of carbon residue on the surface, and the oxidation degree of cerium oxide. On the contrary, the second growth stage is characterized by a constant growth per cycle in good agreement with the literature, low carbon residues, and almost fully oxidized cerium oxide films. This distinction between two growth regimes is not unique to the CeOx/SiO2 system but can be generalized to other metal oxide substrates. Furthermore, the film growth deviates from the ideal layer-by-layer mode, forming micrometric inhomogeneous and defective flakes that eventually coalesce for deposit thicknesses above 10 nm. The ALD-cerium oxide films present less order and a higher density of defects than films grown by physical vapor deposition techniques, likely affecting their reactivity in oxidizing and reducing conditions.},
language = {en}
}
@misc{MaldonadoAcalOrtizetal.,
author = {Maldonado, D. and Acal, C. and Ortiz, H. and Aguilera, A.M. and Ruiz-Castro, J.E. and Cantudo, A. and Baroni, A. and Dorai Swamy Reddy, K. and Pechmann, S. and Uhlmann, M. and Wenger, Christian and P{\´e}rez, E. and Rold{\´a}n, J.B.},
title = {A comprehensive statistical study of the post-programming conductance drift in HfO2-based memristive devices},
series = {Materials science in semiconductor processing},
volume = {196},
journal = {Materials science in semiconductor processing},
publisher = {Elsevier BV},
address = {Amsterdam},
issn = {1369-8001},
doi = {10.1016/j.mssp.2025.109668},
pages = {1 -- 8},
abstract = {The conductance drift in HfO2-based memristors is a critical reliability concern that impacts in their application in non-volatile memory and neuromorphic computing integrated circuits. In this work we present a comprehensive statistical analysis of the conductance drift behavior in resistive random access memories (RRAM) whose physics is based on valence change mechanisms. We experimentally characterize the conductance time evolution in six different resistance states and analyze the suitability of various probability distributions to model the observed variability. Our results reveal that the log-logistic probability distribution provides the best fit to the experimental data for the resistance multilevels and the measured post-programming times under consideration. Additionally, we employ an analysis of variance (ANOVA) to statistically analyze the post-programming time and current level effects on the observed variability. Finally, in the context of the Stanford compact model, we describe how variability has to be implemented to obtain the probability distribution of measured current values.},
language = {en}
}
@misc{SchlipfCutoloManganellietal.,
author = {Schlipf, Jon and Cutolo, Maria Alessandra and Manganelli, Costanza Lucia and Reiter, Sebastian and Seibold, G{\"o}tz and Skibitzki, Oliver and Wenger, Christian and Fischer, Inga Anita},
title = {Fabrication and optical characterization of CMOS-compatible honeycomb-like large-scale lattices of near-field coupled plasmonic TiN nanotriangles},
series = {Advanced optical materials},
volume = {2025},
journal = {Advanced optical materials},
publisher = {Wiley-VCH},
address = {Weinheim},
issn = {2195-1071},
doi = {10.1002/adom.202403408},
pages = {1 -- 8},
abstract = {Honeycomb-like plasmonic titanium nitride nanotriangle arrays defined by photolithography and fabricated in a modified silicon-germanium electronic-photonic integrated circuit process in a state-of-the-art pilot line. The nanotriangle arrays are characterized in experiments and simulations. The momentum-dependent reflectance spectra exhibit not only features that are consistent with surface lattice resonances in the honeycomb lattice but also minima governed by near-field coupling of the individual nanotriangles. The optical characterization results in combination with simulation-based predictions indicate that such nanotriangle arrays are capable of supporting collective plasmonic resonances that can be described as massless Dirac particles. The fabrication approach opens up the possibility of integrating the structures into device fabrication processes, and avenues toward near-infrared sensing and communication applications are predicted.},
language = {en}
}
@misc{RajuDubeyLukoseetal.,
author = {Raju, Ashraful Islam and Dubey, Pawan Kumar and Lukose, Rasuole and Wenger, Christian and Mai, Andreas and Lukosius, Mindaugas},
title = {Optimized silicon nitride-spaced graphene electro-optic modulator with high efficiency and bandwidth},
series = {Optical and quantum electronics},
volume = {57},
journal = {Optical and quantum electronics},
number = {7},
publisher = {Springer Science and Business Media LLC},
address = {Dordrecht},
issn = {1572-817X},
doi = {10.1007/s11082-025-08310-0},
pages = {1 -- 15},
abstract = {Optical modulators with high modulation efficiency, large operational bandwidth, high-speed and low energy consumption is essential for the advancement of on-chip optical signal processing. To overcome the bandwidth-efficiency trade-off in graphene optical modulators, a buried silicon nitride waveguide-coupled double-layer graphene electro-absorption (EA) optical modulator has been proposed. In the proposed design, silicon nitride layer is also embedded between the two graphene layers as a dielectric spacer to enhance the graphene-light interaction. An extensive simulation has been performed to optimize the dielectric spacing layers between the two graphene for optimal device performance including the waveguide dimensions and optical modes profile. The simulated results show a high modulation efficiency of 1.1 dB/V and a modulation depth of 0.16 dB/µm, corresponding to a 15-dB extinction ratio for a 100 µm device at 1550 nm, with a 30 nm spacer and 12 V driving voltage. The proposed modulator achieves a 14 GHz bandwidth and operates over a 1050 nm broadband operation spectral range. The concurrent presence of high modulation bandwidth and efficiency renders these modulator designs highly viable for on-chip optical communication applications.},
language = {en}
}
@misc{MoralesTschammerPożarowskaetal.,
author = {Morales, Carlos and Tschammer, Rudi and Pożarowska, Emilia and Kosto, Julia and Villar-Garcia, Ignacio J. and P{\´e}rez-Dieste, Virginia and Favaro, Marco and Starr, David E. and Kapuścik, Paulina and Mazur, Michał and Wojcieszak, Damian and Domaradzki, Jarosław and Alvarado, Carlos and Wenger, Christian and Henkel, Karsten and Flege, Jan Ingo},
title = {Hydrogen sensing via heterolytic H₂ activation at room temperature by atomic layer deposited ceria},
series = {ChemSusChem : chemistry, sustainability, energy, materials},
volume = {18},
journal = {ChemSusChem : chemistry, sustainability, energy, materials},
number = {13},
publisher = {Wiley-VCH},
address = {Weinheim},
issn = {1864-5631},
doi = {10.1002/cssc.202402342},
pages = {1 -- 13},
abstract = {Ultrathin atomic layer deposited ceria films (\<20 nm) are capable of H2 heterolytic activation at room temperature, undergoing a significant reduction regardless of the absolute pressure, as measured under in-situ conditions by near ambient pressure X-ray photoelectron spectroscopy. ALD-ceria can gradually reduce as a function of H2 concentration under H2/O2 environments, especially for diluted mixtures below 10 \%. At room temperature, this reduction is limited to the surface region, where the hydroxylation of the ceria surface induces a charge transfer towards the ceria matrix, reducing Ce4+ cations to Ce3+. Thus, ALD-ceria replicates the expected sensing mechanism of metal oxides at low temperatures without using any noble metal decorating the oxide surface to enhance H2 dissociation. The intrinsic defects of the ALD deposit seem to play a crucial role since the post-annealing process capable of healing these defects leads to decreased film reactivity. The sensing behavior was successfully demonstrated in sensor test structures by resistance changes towards low concentrations of H2 at low operating temperatures without using noble metals. These promising results call for combining ALD-ceria with more conductive metal oxides, taking advantage of the charge transfer at the interface and thus modifying the depletion layer formed at the heterojunction.},
language = {en}
}
@misc{FuenningPaulManganellietal.,
author = {F{\"u}nning, Tabea and Paul, Martin and Manganelli, Costanza Lucia and Wenger, Christian and Mai, Andreas and Steglich, Patrick},
title = {Comparative simulation analysis of photonic ultrasound sensors based on silicon waveguides},
series = {Scientific reports},
volume = {15},
journal = {Scientific reports},
number = {1},
publisher = {Springer Science and Business Media LLC},
address = {[London]},
issn = {2045-2322},
doi = {10.1038/s41598-025-01953-9},
pages = {1 -- 13},
abstract = {Pressure sensors based on photonic integrated circuits (PIC) offer the prospect of outstanding sensitivities, extreme miniaturization and have the potential for highly scalable production using CMOS compatible processing. PIC-based pressure sensors detect the change in optical properties, i.e. the intensity or phase of the optical carrier wave inside miniaturized waveguide structures. The detection of ultrasound is achieved by engineering the waveguide architecture such that a pressure causes a high change in the effective refractive index of the waveguide. A range of PIC-based pressure sensors have been reported, but a comparison of the sensitivity of the different approaches is not straightforward, since different pressure sensitive waveguide architectures as well as photonic layouts and measurement setups impact the performance. Additionally, the used sensitivity unit is not uniform throughout the different studies, further complicating a comparison. In this work, a detailed simulation study is carried out by finite element modeling of different pressure sensitive waveguide architectures for a consistent comparison. We analyze three different sensor architectures: (A) a free standing membrane located within a tiny air gap above the waveguide, (B) a waveguide located on top of a deflectable membrane as well as (C) a waveguide embedded inside a pressure-sensitive polymer cladding. The mechanical response of the structures and the resulting changes in mode propagation, i.e. the change of the effective refractive index, are analyzed. The waveguide sensitivities in RIU/MPa for different waveguide types (strip, slot) and polarization states (TE, TM) are compared. The results reveal inherent limitations of the different waveguide designs and create a basis for the selection of suitable designs for further ultrasound sensor development. Possibilities for enhancing waveguide sensitivity are identified and discussed. Additionally, we have shown that the studied approaches are extensible to SiN waveguides.},
language = {en}
}
@misc{UhlmannKrysikWenetal.,
author = {Uhlmann, Max and Krysik, Milosz and Wen, Jianan and Frohberg, Max and Baroni, Andrea and Reddy, Keerthi Dorai Swamy and P{\´e}rez, Eduardo and Ostrovskyy, Philip and Piotrowski, Krzysztof and Carta, Corrado and Wenger, Christian and Kahmen, Gerhard},
title = {A compact one-transistor-multiple-RRAM characterization platform},
series = {IEEE transactions on circuits and systems I : regular papers},
journal = {IEEE transactions on circuits and systems I : regular papers},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
address = {New York},
issn = {1549-8328},
doi = {10.1109/TCSI.2025.3555234},
pages = {1 -- 12},
abstract = {Emerging non-volatile memories (eNVMs) such as resistive random-access memory (RRAM) offer an alternative solution compared to standard CMOS technologies for implementation of in-memory computing (IMC) units used in artificial neural network (ANN) applications. Existing measurement equipment for device characterisation and programming of such eNVMs are usually bulky and expensive. In this work, we present a compact size characterization platform for RRAM devices, including a custom programming unit IC that occupies less than 1 mm2 of silicon area. Our platform is capable of testing one-transistor-one-RRAM (1T1R) as well as one-transistor-multiple-RRAM (1TNR) cells. Thus, to the best knowledge of the authors, this is the first demonstration of an integrated programming interface for 1TNR cells. The 1T2R IMC cells were fabricated in the IHP's 130 nm BiCMOS technology and, in combination with other parts of the platform, are able to provide more synaptic weight resolution for ANN model applications while simultaneously decreasing the energy consumption by 50 \%. The platform can generate programming voltage pulses with a 3.3 mV accuracy. Using the incremental step pulse with verify algorithm (ISPVA) we achieve 5 non-overlapping resistive states per 1T1R device. Based on those 1T1R base states we measure 15 resulting state combinations in the 1T2R cells.},
language = {en}
}