@misc{NitschRatzkePozarowskaetal.,
author = {Nitsch, Paul-G. and Ratzke, Markus and Pozarowska, Emilia and Flege, Jan Ingo and Alvarado Chavarin, Carlos and Wenger, Christian and Fischer, Inga Anita},
title = {Deposition of reduced ceria thin films by reactive magnetron sputtering for the development of a resistive gas sensor},
series = {Verhandlungen der DPG, Berlin 2024},
journal = {Verhandlungen der DPG, Berlin 2024},
publisher = {Deutsche Physikalische Gesellschaft},
address = {Bad Honnef},
issn = {0420-0195},
abstract = {The use of cerium oxide for hydrogen sensing is limited by the low electrical conductivity of layers deposited from a ceria target. To increase the electrical conductivity, partially reduced cerium oxide layers were obtained from a metallic cerium target by reactive magnetron sputtering. The proportions of the oxidation states Ce3+, present in reduced species, and Ce4+, present in fully oxidized species, were determined by ex-situ XPS. For electrical characterization, films were deposited on planarized tungsten finger electrodes. IV curves were measured over several days to investigate possible influences of oxygen and humidity on electrical conductivity. The morphological stability of the layers under ambient conditions was investigated by microscopical methods. The XPS results show a significant amount of Ce3+ in the layers. The electrical conductivity of as-grown samples is several orders of magnitude higher than that of samples grown from a ceria target. However, the conductivity decreases over time, indicating an oxidation of the layers. The surface morphology of the samples was found to be changing drastically within days, leading to partial delamination.},
language = {en}
}
@misc{StrobelAlvaradoChavarinKnautetal.,
author = {Strobel, Carsten and Alvarado Chavarin, Carlos and Knaut, Martin and V{\"o}lkel, Sandra and Albert, Matthias and Hiess, Andre and Max, Benjamin and Wenger, Christian and Kirchner, Robert and Mikolajick, Thomas},
title = {High Gain Graphene Based Hot Electron Transistor with Record High Saturated Output Current Density},
series = {Advanced Electronic Materials},
volume = {10},
journal = {Advanced Electronic Materials},
number = {2},
issn = {2199-160X},
doi = {10.1002/aelm.202300624},
abstract = {Hot electron transistors (HETs) represent an exciting frontier in semiconductor technology, holding the promise of high-speed and high-frequency electronics. With the exploration of two-dimensional materials such as graphene and new device architectures, HETs are poised to revolutionize the landscape of modern electronics. This study highlights a novel HET structure with a record output current density of 800 A/cm² and a high current gain α, fabricated using a scalable fabrication approach. The HET structure comprises two-dimensional hexagonal boron nitride (hBN) and graphene layers wet transferred to a germanium substrate. The combination of these materials results in exceptional performance, particularly in terms of the highly saturated output current density. The scalable fabrication scheme used to produce the HET opens up opportunities for large-scale manufacturing. This breakthrough in HET technology holds promise for advanced electronic applications, offering high current capabilities in a practical and manufacturable device.},
language = {en}
}
@misc{PechmannPerezWengeretal.,
author = {Pechmann, Stefan and P{\´e}rez, Eduardo and Wenger, Christian and Hagelauer, Amelie},
title = {A current mirror Based read circuit design with multi-level capability for resistive switching deviceb},
series = {2024 International Conference on Electronics, Information, and Communication (ICEIC)},
journal = {2024 International Conference on Electronics, Information, and Communication (ICEIC)},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
isbn = {979-8-3503-7188-8},
issn = {2767-7699},
doi = {10.1109/ICEIC61013.2024.10457188},
pages = {4},
abstract = {This paper presents a read circuit design for resistive memory cells based on current mirrors. The circuit utilizes high-precision current mirrors and reference cells to determine the state of resistive memory using comparators. It offers a high degree in adaptability in terms of both resistance range and number of levels. Special emphasis was put on device protection to prevent accidental programming of the memory during read operations. The realized circuit can resolve eight states with a resolution of up to 1 k Ω, realizing a digitization of the analog memory information. Furthermore, the integration in a complete memory macro is shown. The circuit was realized in a 130 nm-process but can easily be adapted to other processes and resistive memory technologies.},
language = {en}
}
@misc{NikiruyPerezBaronietal.,
author = {Nikiruy, Kristina and P{\´e}rez, Eduardo and Baroni, Andrea and Dorai Swamy Reddy, Keerthi and Pechmann, Stefan and Wenger, Christian and Ziegler, Martin},
title = {Blooming and pruning: learning from mistakes with memristive synapses},
series = {Scientific Reports},
volume = {14},
journal = {Scientific Reports},
number = {1},
issn = {2045-2322},
doi = {10.1038/s41598-024-57660-4},
abstract = {AbstractBlooming and pruning is one of the most important developmental mechanisms of the biological brain in the first years of life, enabling it to adapt its network structure to the demands of the environment. The mechanism is thought to be fundamental for the development of cognitive skills. Inspired by this, Chialvo and Bak proposed in 1999 a learning scheme that learns from mistakes by eliminating from the initial surplus of synaptic connections those that lead to an undesirable outcome. Here, this idea is implemented in a neuromorphic circuit scheme using CMOS integrated HfO2-based memristive devices. The implemented two-layer neural network learns in a self-organized manner without positive reinforcement and exploits the inherent variability of the memristive devices. This approach provides hardware, local, and energy-efficient learning. A combined experimental and simulation-based parameter study is presented to find the relevant system and device parameters leading to a compact and robust memristive neuromorphic circuit that can handle association tasks.},
language = {en}
}
@inproceedings{WenVargasZhuetal.,
author = {Wen, Jianan and Vargas, Fabian Luis and Zhu, Fukun and Reiser, Daniel and Baroni, Andrea and Fritscher, Markus and P{\´e}rez, Eduardo and Reichenbach, Marc and Wenger, Christian and Krstic, Milos},
title = {Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment},
series = {2024 IEEE 25th Latin American Test Symposium (LATS)},
booktitle = {2024 IEEE 25th Latin American Test Symposium (LATS)},
publisher = {IEEE},
doi = {10.1109/LATS62223.2024.10534601},
pages = {6},
abstract = {Emerging device technologies such as resistive RAM (RRAM) are increasingly recognized in enhancing system performance, particularly in applications demanding extensive vector-matrix multiplications (VMMs) with high parallelism. However, a significant limitation in current electronics design automation (EDA) tools is their lack of support for rapid prototyping, design space exploration, and the integration of inherent process-dependent device variability into system-level simulations, which is essential for assessing system reliability. To address this gap, we introduce a field-programmable gate array (FPGA) based emulation approach for RRAM crossbars featuring cycle-accurate emulations in real time without relying on complex device models. Our approach is based on pre-generated look-up tables (LUTs) to accurately represent the RRAM device behavior. To efficiently model the device variability at the system level, we propose using the multivariate kernel density estimation (KDE) method to augment the measured RRAM data. The proposed emulator allows precise latency determination for matrix mapping and computation operations. Meanwhile, by coupling with the NeuroSim framework, the corresponding energy consumption can be estimated. In addition to facilitating a range of in-depth system assessments, experimental results suggest a remarkable reduction of emulation time compared to the classic behavioral simulation.},
language = {en}
}
@misc{DoraiSwamyReddyPerezBaronietal.,
author = {Dorai Swamy Reddy, Keerthi and P{\´e}rez, Eduardo and Baroni, Andrea and Mahadevaiah, Mamathamba Kalishettyhalli and Marschmeyer, Steffen and Fraschke, Mirko and Lisker, Marco and Wenger, Christian and Mai, Andreas},
title = {Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance},
series = {The European Physical Journal B},
volume = {97},
journal = {The European Physical Journal B},
publisher = {Springer Science and Business Media LLC},
issn = {1434-6028},
doi = {10.1140/epjb/s10051-024-00821-1},
pages = {9},
abstract = {Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal-insulator-metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2 dielectric thickness from 8 nm to 5 nm. Additionally, 5\% Al-doped 4 nm HfO2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology.},
language = {en}
}
@misc{JiaPechmannMarkusetal.,
author = {Jia, Ruolan and Pechmann, Stefan and Markus, Fritscher and Wenger, Christian and Zhang, Lei and Hagelauer, Amelie},
title = {Soft-Error Analysis of RRAM 1T1R Compute-In-Memory Core for Artificial Neural Networks},
series = {2024 39th Conference on Design of Circuits and Integrated Systems (DCIS)},
journal = {2024 39th Conference on Design of Circuits and Integrated Systems (DCIS)},
publisher = {IEEE},
doi = {10.1109/DCIS62603.2024.10769203},
pages = {1 -- 5},
abstract = {This work analyses SEU-induced soft-errors in analog compute-in-memory cores using resistive random-access memory (RRAM) for artificial neural networks, where their bitcells utilize one-transistor-one-RRAM (1T1R) structure. This is modeled by combining the Stanford-PKU RRAM Model and the model of the radiation-induced photocurrent in access transistors. As results, this work derives the maximal RRAM crossbar size without occurring any logic flip and indicates the requirements for RRAM technology to achieve a SEU-resilient 1T1R compute-in memory cores.},
language = {en}
}
@misc{PerezBoschQuesadaMistroniJiaetal.,
author = {Perez-Bosch Quesada, Emilio and Mistroni, Alberto and Jia, Ruolan and Dorai Swamy Reddy, Keerthi and Reichmann, Felix and Castan, Helena and Due{\~n}as, Salvador and Wenger, Christian and Perez, Eduardo},
title = {Forming and resistive switching of HfO₂-based RRAM devices at cryogenic temperature},
series = {IEEE Electron Device Letters},
volume = {45},
journal = {IEEE Electron Device Letters},
number = {12},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
issn = {0741-3106},
doi = {10.1109/LED.2024.3485873},
pages = {2391 -- 2394},
abstract = {Reliable data storage technologies able to operate at cryogenic temperatures are critical to implement scalable quantum computers and develop deep-space exploration systems, among other applications. Their scarce availability is pushing towards the development of emerging memories that can perform such storage in a non-volatile fashion. Resistive Random-Access Memories (RRAM) have demonstrated their switching capabilities down to 4K. However, their operability at lower temperatures still remain as a challenge. In this work, we demonstrate for the first time the forming and resistive switching capabilities of CMOS-compatible RRAM devices at 1.4K. The HfO2-based devices are deployed following an array of 1-transistor-1-resistor (1T1R) cells. Their switching performance at 1.4K was also tested in the multilevel-cell (MLC) approach, storing up to 4 resistance levels per cell.},
language = {en}
}
@misc{WeisshauptSuergersBloosetal.,
author = {Weißhaupt, David and S{\"u}rgers, Christoph and Bloos, Dominik and Funk, Hannes Simon and Oehme, Michael and Fischer, Gerda and Schubert, Markus Andreas and Wenger, Christian and van Slageren, Joris and Fischer, Inga Anita and Schulze, J{\"o}rg},
title = {Lateral Mn5Ge3 spin-valve in contact with a high-mobility Ge two-dimensional hole gas},
series = {Semiconductor Science and Technology},
volume = {39},
journal = {Semiconductor Science and Technology},
number = {12},
publisher = {IOP Publishing},
issn = {0268-1242},
doi = {10.1088/1361-6641/ad8d06},
pages = {1 -- 10},
abstract = {Abstract Ge two-dimensional hole gases (2DHG) in strained modulation-doped quantum-wells represent a promising material platform for future spintronic applications due to their excellent spin transport properties and the theoretical possibility of efficient spin manipulation. Due to the continuous development of epitaxial growth recipes extreme high hole mobilities and low effective masses can be achieved, promising an efficient spin transport. Furthermore, the Ge 2DHG can be integrated in the well-established industrial complementary metal-oxide-semiconductor (CMOS) devices technology. However, efficient electrical spin injection into a Ge 2DHG—an essential prerequisite for the realization of spintronic devices—has not yet been demonstrated. In this work, we report the fabrication and low-temperature magnetoresistance (MR) measurements of a laterally structured Mn5Ge3/Ge 2DHG/ Mn5Ge3 device. The ferromagnetic Mn5Ge3 contacts are grown directly into the Ge quantum well by means of an interdiffusion process with a spacing of approximately 130 nm, forming a direct electrical contact between the ferromagnetic metal and the Ge 2DHG. Here, we report for the first time a clear MR signal for temperatures below 13 K possibly arising from successful spin injection into the high mobility Ge 2DHG. The results represent a step forward toward the realization of CMOS compatible spintronic devices based on a 2DHG.},
language = {en}
}
@misc{CapistaLukoseMajnoonetal.,
author = {Capista, Daniele and Lukose, Rasuole and Majnoon, Farnaz and Lisker, Marco and Wenger, Christian and Lukosius, Mindaugas},
title = {Optimization of the metal deposition process for the accurate estimation of Low Metal-Graphene Contact-Resistance},
series = {47th MIPRO ICT and Electronics Convention (MIPRO), 20-24 May 2024, Opatija, Croatia},
journal = {47th MIPRO ICT and Electronics Convention (MIPRO), 20-24 May 2024, Opatija, Croatia},
isbn = {979-8-3503-8250-1},
issn = {2623-8764},
doi = {10.1109/MIPRO60963.2024.10569895},
pages = {5},
language = {en}
}
@misc{MaldonadoCantudoSwamyReddyetal.,
author = {Maldonado, David and Cantudo, Antonio and Swamy Reddy, Keerthi Dorai and Pechmann, Stefan and Uhlmann, Max and Wenger, Christian and Roldan, Juan Bautista and P{\´e}rez, Eduardo},
title = {Influence of stop and gate voltage on resistive switching of 1T1R HfO2-based memristors, a modeling and variability analysis},
series = {Materials Science in Semiconductor Processing},
volume = {182},
journal = {Materials Science in Semiconductor Processing},
issn = {1873-4081},
doi = {10.1016/j.mssp.2024.108726},
pages = {9},
language = {en}
}
@misc{KostoTschammerMoralesetal.,
author = {Kosto, Yuliia and Tschammer, Rudi and Morales, Carlos and Henkel, Karsten and Flege, Jan Ingo and Ratzke, Markus and Fischer, Inga Anita and Costina, Ioan and Alvarado Chavarin, Carlos and Wenger, Christian},
title = {Rational design and development of room temperature hydrogen sensors compatible with CMOS technology: a necessary step for the coming renewable hydrogen economy},
series = {Proceedings of iCampus Conference Cottbus 2024},
journal = {Proceedings of iCampus Conference Cottbus 2024},
publisher = {AMA Service GmbH},
address = {Wunstorf},
isbn = {978-3-910600-00-3},
doi = {10.5162/iCCC2024/P21},
pages = {182 -- 185},
abstract = {The transition towards a new, renewable energy system based on green energy vectors, such as hydrogen, requires not only direct energy conversion and storage systems, but also the development of auxiliary components, such as highly sensitive hydrogen gas sensors integrated into mass devices that operate at ambient conditions. Despite the recent advances in nanostructured metal oxide thin films in terms of simple fabrication processes and compatibility with integrated circuits, high sensitivity, and short response/recovery times usually require the use of expensive noble metals or elevated tem-peratures (>250 ºC), which results in high power consumption and poor long-term stability. This article presents the first steps of the work on developing a novel resistive hydrogen gas sensor based on ultrathin cerium oxide films, compatible with complementary metal oxide semiconductor technology and capable of operating at room temperature. Here, we show a multidisciplinary bottom-up approach combining different work areas for the sensor development, such as sensor architecture, sensing mechanism and deposition strategy of the active layer, electrical contact design depending on the desired electrical output, and fast testing under controlled environments.},
language = {en}
}
@misc{VinuesaGarciaPerezetal.,
author = {Vinuesa, Guillermo and Garc{\´i}a, H{\´e}ctor and P{\´e}rez, Eduardo and Wenger, Christian and {\´I}{\~n}iguez de la Torre, Ignacio and Gonz{\´a}lez, Tom{\´a}s and Due{\~n}as, Salvador and Cast{\´a}n, Helena},
title = {On the asymmetry of Resistive Switching Transitions},
series = {Electronics},
volume = {13},
journal = {Electronics},
number = {13},
publisher = {MDPI},
issn = {2079-9292},
doi = {10.3390/electronics13132639},
pages = {11},
abstract = {In this study, the resistive switching phenomena in TiN/Ti/HfO2/Ti metal-insulator-metal stacks is investigated, mainly focusing on the analysis of set and reset transitions. The electrical measurements in a wide temperature range reveal that the switching transitions require less voltage (and thus, less energy) as temperature rises, with the reset process being much more temperature sensitive. The main conduction mechanism in both resistance states is Space-charge-limited Conduction, but the high conductivity state also shows Schottky emission, explaining its temperature dependence. Moreover, the temporal evolution of these transitions reveals clear differences between them, as their current transient response is completely different. While the set is sudden, the reset process development is clearly non-linear, closely resembling a sigmoid function. This asymmetry between switching processes is of extreme importance in the manipulation and control of the multi-level characteristics and has clear implications in the possible applications of resistive switching devices in neuromorphic computing.},
language = {en}
}
@misc{StrobelAlvaradoChavarinKnautetal.,
author = {Strobel, Carsten and Alvarado Chavarin, Carlos and Knaut, Martin and Albert, Matthias and Heinzig, Andr{\´e} and Gummadi, Likhith and Wenger, Christian and Mikolajick, Thomas},
title = {p-Type Schottky contacts for graphene adjustable-Barrier phototransistors},
series = {Nanomaterials},
volume = {14},
journal = {Nanomaterials},
number = {13},
editor = {Giannazzo, Filippo and Agnello, Simonpietro and Seravalli, Luca and Bondino, Federica},
publisher = {MDPI},
issn = {2079-4991},
doi = {10.3390/nano14131140},
abstract = {The graphene adjustable-barriers phototransistor is an attractive novel device for potential high speed and high responsivity dual-band photodetection. In this device, graphene is embedded between the semiconductors silicon and germanium. Both n-type and p-type Schottky contacts between graphene and the semiconductors are required for this device. While n-type Schottky contacts are widely investigated, reports about p-type Schottky contacts between graphene and the two involved semiconductors are scarce. In this study, we demonstrate a p-type Schottky contact between graphene and p-germanium. A clear rectification with on-off ratios of close to 10 3 (±5 V) and a distinct photoresponse at telecommunication wavelengths in the infrared are achieved. Further, p-type silicon is transferred to or deposited on graphene, and we also observe rectification and photoresponse in the visible range for some of these p-type Schottky junctions. These results are an important step toward the realization of functional graphene adjustable-barrier phototransistors.},
language = {en}
}
@misc{MoralesPlateMarthetal.,
author = {Morales, Carlos and Plate, Paul and Marth, Ludwig and Naumann, Franziska and Kot, Małgorzata and Janowitz, Christoph and Kus, Peter and Z{\"o}llner, Marvin Hartwig and Wenger, Christian and Henkel, Karsten and Flege, Jan Ingo},
title = {Bottom-up design of a supercycle recipe for atomic layer deposition of tunable Indium Gallium Zinc Oxide thin films},
series = {ACS Applied Electronic Materials},
volume = {6},
journal = {ACS Applied Electronic Materials},
number = {8},
publisher = {American Chemical Society (ACS)},
issn = {2637-6113},
doi = {10.1021/acsaelm.4c00730},
pages = {5694 -- 5704},
abstract = {We present a successful bottom-up approach to design a generic plasma-enhanced atomic layer deposition (PEALD) supercycle recipe to grow high-quality indium gallium zinc oxide (IGZO) thin films with tunable composition at a relatively low temperature of 150 °C. In situ real-time ellipsometric characterization in combination with ex situ complementary techniques has been used to optimize the deposition process and quality of the films by identifying and solving growth challenges such as degree of oxidation, nucleation delays, or elemental composition. The developed supercycle approach enables facile control of the target composition by adapting the subcycle ratios within the supercycle process. Compared to other low-temperature deposition techniques resulting in amorphous films, our PEALD-IGZO process at 150 °C results in nearly amorphous, nanocrystalline films. The preparation of IGZO films at low temperature by a supercycle PEALD approach allows controlling the thickness, composition, and electrical properties while preventing thermally induced segregation.},
language = {en}
}
@misc{HayatRatzkeAlvaradoChavarinetal.,
author = {Hayat, Ahsan and Ratzke, Markus and Alvarado Chavarin, Carlos and Z{\"o}llner, Marvin Hartwig and Corley-Wiciak, Agnieszka Anna and Schubert, Markus Andreas and Wenger, Christian and Fischer, Inga Anita},
title = {Structural and morphological properties of CeO2 films deposited by radio frequency magnetron sputtering for back-end-of-line integration},
series = {Thin Solid Films},
volume = {807},
journal = {Thin Solid Films},
issn = {0040-6090},
doi = {10.1016/j.tsf.2024.140547},
pages = {3},
language = {en}
}
@misc{FritscherSinghRizzietal.,
author = {Fritscher, Markus and Singh, Simranjeet and Rizzi, Tommaso and Baroni, Andrea and Reiser, Daniel and Mallah, Maen and Hartmann, David and Bende, Ankit and Kempen, Tim and Uhlmann, Max and Kahmen, Gerhard and Fey, Dietmar and Rana, Vikas and Menzel, Stephan and Reichenbach, Marc and Krstic, Milos and Merchant, Farhad and Wenger, Christian},
title = {A flexible and fast digital twin for RRAM systems applied for training resilient neural networks},
series = {Scientific Reports},
volume = {14},
journal = {Scientific Reports},
number = {1},
publisher = {Springer Science and Business Media LLC},
issn = {2045-2322},
doi = {10.1038/s41598-024-73439-z},
pages = {13},
abstract = {Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the "ideal memristor" which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a "push button" modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).},
language = {en}
}
@misc{LukosiusLukoseDubeyetal.,
author = {Lukosius, Mindaugas and Lukose, Rasuolė and Dubey, P. K. and Raju, A. I. and Capista, Daniele and Lisker, Marco and Mai, A. and Wenger, Christian},
title = {Graphene for photonic applications},
series = {2024 47th MIPRO ICT and Electronics Convention (MIPRO)},
journal = {2024 47th MIPRO ICT and Electronics Convention (MIPRO)},
publisher = {IEEE},
isbn = {979-8-3503-8250-1},
issn = {2623-8764},
doi = {10.1109/MIPRO60963.2024.10569652},
pages = {1614 -- 1618},
abstract = {Integrating graphene into Silicon Complementary Metal-Oxide-Semiconductor (CMOS) technology for photonic applications holds immense promise, but it encounters challenges in establishing large-scale graphene processes. These challenges encompass growth through techniques like Chemical Vapor Deposition (CVD), transfer, encapsulation, and contact formation within a routine 200mm wafer pilot line typically utilized for integrated circuit fabrication. This study is dedicated to exploring various facets of graphene research within a 200 mm pilot line, with a focus on overcoming challenges through the fabrication of proof-of-concept photonic graphene-based devices. The synthesis of graphene targeted epi-Ge(100)/Si(100) substrates, grown within the IHP pilot line, showcasing the potential for high-quality graphene deposition across 200mm wafers. Alternatively, employing different orientations such as (110) has been explored to enhance graphene mobility, achieving a remarkable mobility of 2300 cm 2 /Vs at present. The study systematically investigates graphene quality, thickness, and homogeneity utilizing techniques such as Raman spectroscopy, Atomic Force Microscopy (AFM), and Scanning Electron Microscopy (SEM). Additionally, simulations and fabrication of the graphene ring modulators have been conducted at both the component and device levels, incorporating realistic graphene properties. These results indicate a modulation depth of 1.6 dB/μm and a 3dB bandwidth of 7 GHz, showcasing the potential of graphene-based photonic devices for high-speed communication applications.},
language = {en}
}
@misc{FritscherWengerKrstic,
author = {Fritscher, Markus and Wenger, Christian and Krstic, Milos},
title = {From device to application - integrating RRAM Accelerator Blocks into large AI systems},
series = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
journal = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
publisher = {IEEE},
isbn = {979-8-3503-5411-9},
issn = {2159-3477},
doi = {10.1109/ISVLSI61997.2024.00111},
pages = {592 -- 592},
abstract = {This work provides an introduction to design methodologies for RRAM-based systems. We illustrate the impact of device variation on the performance of neural networks and propose a circuit-level integration approach for RRAM-based compute blocks. Moreover, we demonstrate a possible architectural integration by incorporating RRAM-based VMM blocks fabricated in a 130 nm CMOS process into a RISC-V.},
language = {en}
}
@misc{FritscherUhlmannOstrovskyyetal.,
author = {Fritscher, Markus and Uhlmann, Max and Ostrovskyy, Philip and Reiser, Daniel and Chen, Junchao and Schubert, Andreas and Schulze, Carsten and Kahmen, Gerhard and Fey, Dietmar and Reichenbach, Marc and Krstic, Milos and Wenger, Christian},
title = {Area-efficient digital design using RRAM-CMOS standard cells},
series = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
volume = {18},
journal = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
publisher = {IEEE},
isbn = {979-8-3503-5411-9},
issn = {2159-3477},
doi = {10.1109/ISVLSI61997.2024.00026},
pages = {81 -- 87},
abstract = {Extending the scalability of digital integrated circuits through novel device concepts is an attractive option. Among these concepts, resistive random access memory (RRAM) devices allow fast and nonvolatile operation. However, building large memristive systems is still challenging since large analog circuits have to be designed and integrated. In this paper, we propose a novel solution - the implementation of digital standard cells by the means of RRAM devices. While this methodology is universal, with applications ranging from few-device-circuits to large macroblocks, we demonstrate it for a 2T2R-cell. The benefits of using RRAM devices are demonstrated by implementing a NAND standard cell merely consuming the area of two transistors. This cell is about 25 \% smaller than the equivalent CMOS NAND in the same technology. We use these cells to implement a half adder, beating the area of the equivalent CMOS implementation using more sophisticates gates by 15 \%. Lastly, we fully integrate this novel standard cell into a digital standard cell library and perform a synthesis and layout of a RISC-V CPU core.},
language = {en}
}