@misc{OssorioVinuesaGarciaetal., author = {Ossorio, {\´O}scar G. and Vinuesa, Guillermo and Garcia, Hector and Sahelices, Benjamin and Duenas, Salvador and Castan, Helena and Perez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Wenger, Christian}, title = {Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications}, series = {ECS Transactions}, volume = {102}, journal = {ECS Transactions}, number = {2}, issn = {1938-6737}, doi = {10.1149/10202.0029ecst}, pages = {29 -- 35}, abstract = {The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.}, language = {en} } @misc{BaroniGlukhovPerezetal., author = {Baroni, Andrea and Glukhov, Artem and Perez, Eduardo and Wenger, Christian and Calore, Enrico and Schifano, Sebastiano Fabio and Olivo, Piero and Ielmini, Daniele and Zambelli, Cristian}, title = {An energy-efficient in-memory computing architecture for survival data analysis based on resistive switching memories}, series = {Frontiers in Neuroscience}, volume = {Vol. 16}, journal = {Frontiers in Neuroscience}, issn = {1662-4548}, doi = {10.3389/fnins.2022.932270}, pages = {1 -- 16}, abstract = {One of the objectives fostered in medical science is the so-called precision medicine, which requires the analysis of a large amount of survival data from patients to deeply understand treatment options. Tools like Machine Learning and Deep Neural Networks are becoming a de-facto standard. Nowadays, computing facilities based on the Von Neumann architecture are devoted to these tasks, yet rapidly hitting a bottleneck in performance and energy efficiency. The In-Memory Computing (IMC) architecture emerged as a revolutionary approach to overcome that issue. In this work, we propose an IMC architecture based on Resistive switching memory (RRAM) crossbar arrays to provide a convenient primitive for matrix-vector multiplication in a single computational step. This opens massive performance improvement in the acceleration of a neural network that is frequently used in survival analysis of biomedical records, namely the DeepSurv. We explored how the synaptic weights mapping strategy and the programming algorithms developed to counter RRAM non-idealities expose a performance/energy trade-off. Finally, we assessed the benefits of the proposed architectures with respect to a GPU-based realization of the same task, evidencing a tenfold improvement in terms of performance and three orders of magnitude with respect to energy efficiency.}, language = {en} } @misc{PerezBoschQuesadaRomeroZalizPerezetal., author = {P{\´e}rez-Bosch Quesada, Emilio and Romero-Zaliz, Roc{\´i}o and Perez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Reuben, John and Schubert, Markus Andreas and Jim{\´e}nez-Molinos, Francisco and Rold{\´a}n, Juan Bautista and Wenger, Christian}, title = {Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems}, series = {Electronics (MDPI)}, volume = {10}, journal = {Electronics (MDPI)}, number = {6}, issn = {2079-9292}, doi = {10.3390/electronics10060645}, pages = {13}, abstract = {In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.}, language = {en} } @misc{PetrykDykaPerezetal., author = {Petryk, Dmytro and Dyka, Zoya and Perez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Kabin, Ievgen and Wenger, Christian and Langend{\"o}rfer, Peter}, title = {Evaluation of the Sensitivity of RRAM Cells to Optical Fault Injection Attacks}, series = {EUROMICRO Conference on Digital System Design (DSD 2020), Special Session: Architecture and Hardware for Security Applications (AHSA)}, journal = {EUROMICRO Conference on Digital System Design (DSD 2020), Special Session: Architecture and Hardware for Security Applications (AHSA)}, isbn = {978-1-7281-9535-3}, issn = {978-1-7281-9536-0}, doi = {10.1109/DSD51259.2020.00047}, pages = {8}, language = {en} } @misc{GlukhovLepriMiloetal., author = {Glukhov, Artem and Lepri, Nicola and Milo, Valerio and Baroni, Andrea and Zambelli, Cristian and Olivo, Piero and Perez, Eduardo and Wenger, Christian and Ielmini, Daniele}, title = {End-to-end modeling of variability-aware neural networks based on resistive-switching memory arrays}, series = {Proc. 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2022)}, journal = {Proc. 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2022)}, doi = {10.1109/VLSI-SoC54400.2022.9939653}, pages = {1 -- 5}, abstract = {Resistive-switching random access memory (RRAM) is a promising technology that enables advanced applications in the field of in-memory computing (IMC). By operating the memory array in the analogue domain, RRAM-based IMC architectures can dramatically improve the energy efficiency of deep neural networks (DNNs). However, achieving a high inference accuracy is challenged by significant variation of RRAM conductance levels, which can be compensated by (i) advanced programming techniques and (ii) variability-aware training (VAT) algorithms. In both cases, however, detailed knowledge and accurate physics-based statistical models of RRAM are needed to develop programming and VAT methodologies. This work presents an end-to-end approach to the development of highly-accurate IMC circuits with RRAM, encompassing the device modeling, the precise programming algorithm, and the VAT simulations to maximize the DNN classification accuracy in presence of conductance variations.}, language = {en} } @misc{PerezOssorioDuenasetal., author = {Perez, Eduardo and Ossorio, {\´O}scar G. and Duenas, Salvador and Castan, Helena and Garc{\´i}a, Hector and Wenger, Christian}, title = {Programming Pulse Width Assessment for Reliable and Low-Energy Endurance Performance in Al:HfO2-Based RRAM Arrays}, series = {Electronics (MDPI)}, volume = {9}, journal = {Electronics (MDPI)}, number = {5}, issn = {2079-9292}, doi = {10.3390/electronics9050864}, abstract = {A crucial step in order to achieve fast and low-energy switching operations in resistive random access memory (RRAM) memories is the reduction of the programming pulse width. In this study, the incremental step pulse with verify algorithm (ISPVA) was implemented by using different pulse widths between 10 μ s and 50 ns and assessed on Al-doped HfO 2 4 kbit RRAM memory arrays. The switching stability was assessed by means of an endurance test of 1k cycles. Both conductive levels and voltages needed for switching showed a remarkable good behavior along 1k reset/set cycles regardless the programming pulse width implemented. Nevertheless, the distributions of voltages as well as the amount of energy required to carry out the switching operations were definitely affected by the value of the pulse width. In addition, the data retention was evaluated after the endurance analysis by annealing the RRAM devices at 150 °C along 100 h. Just an almost negligible increase on the rate of degradation of about 1 μ A at the end of the 100 h of annealing was reported between those samples programmed by employing a pulse width of 10 μ s and those employing 50 ns. Finally, an endurance performance of 200k cycles without any degradation was achieved on 128 RRAM devices by using programming pulses of 100 ns width}, language = {en} } @misc{PetzoldPirosEilhardtetal., author = {Petzold, Stefan and Piros, Eszter and Eilhardt, Robert and Zintler, Alexander and Vogel, Tobias and Kaiser, Nico and Radetinac, Aldin and Komissinskiy, Philipp and Jalaguier, Eric and Nolot, Emmanuel and Charpin-Nicolle, Christelle and Wenger, Christian and Molina-Luna, Leopoldo and Miranda, Enrique and Alff, Lambert}, title = {Tailoring the Switching Dynamics in Yttrium Oxide-Based RRAM Devices by Oxygen Engineering: From Digital to Multi-Level Quantization toward Analog Switching}, series = {Advanced Electronic Materials}, volume = {6}, journal = {Advanced Electronic Materials}, number = {11}, issn = {2199-160X}, doi = {10.1002/aelm.202000439}, pages = {13}, abstract = {This work investigates the transition from digital to gradual or analog resistive switching in yttrium oxide-based resistive random-access memory devices. It is shown that this transition is determined by the amount of oxygen in the functional layer. A homogeneous reduction of the oxygen content not only reduces the electroforming voltage, allowing for forming-free devices, but also decreases the voltage operation window of switching, thereby reducing intra-device variability. The most important effect as the dielectric becomes substoichiometric by oxygen engineering is that more intermediate (quantized) conduction states are accessible. A key factor for this reproducibly controllable behavior is the reduced local heat dissipation in the filament region due to the increased thermal conductivity of the oxygen depleted layer. The improved accessibility of quantized resistance states results in a semi-gradual switching both for the set and reset processes, as strongly desired for multi-bit storage and for an accurate definition of the synaptic weights in neuromorphic systems. A theoretical model based on the physics of mesoscopic structures describing current transport through a nano-constriction including asymmetric potential drops at the electrodes and non-linear conductance quantization is provided. The results contribute to a deeper understanding on how to tailor materials properties for novel memristive functionalities.}, language = {en} } @misc{GlukhovMiloBaronietal., author = {Glukhov, Artem and Milo, Valerio and Baroni, Andrea and Lepri, Nicola and Zambelli, Cristian and Olivo, Piero and Perez, Eduardo and Wenger, Christian and Ielmini, Daniele}, title = {Statistical model of program/verify algorithms in resistive-switching memories for in-memory neural network accelerators}, series = {2022 IEEE International Reliability Physics Symposium (IRPS)}, journal = {2022 IEEE International Reliability Physics Symposium (IRPS)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {978-1-6654-7950-9}, issn = {2473-2001}, doi = {10.1109/IRPS48227.2022.9764497}, pages = {3C.3-1 -- 3C.3-7}, abstract = {Resistive-switching random access memory (RRAM) is a promising technology for in-memory computing (IMC) to accelerate training and inference of deep neural networks (DNNs). This work presents the first physics-based statistical model describing (i) multilevel RRAM device program/verify (PV) algorithms by controlled set transition, (ii) the stochastic cycle-to-cycle (C2C) and device-to-device (D2D) variations within the array, and (iii) the impact of such imprecisions on the accuracy of DNN accelerators. The model can handle the full chain from RRAM materials/device parameters to the DNN performance, thus providing a valuable tool for device/circuit codesign of hardware DNN accelerators.}, language = {en} } @misc{PerezBoschQuesadaMahadevaiahRizzietal., author = {Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Rizzi, Tommaso and Wen, Jianan and Ulbricht, Markus and Krstic, Milos and Wenger, Christian and Perez, Eduardo}, title = {Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing}, series = {IEEE Transactions on Electron Devices}, volume = {70}, journal = {IEEE Transactions on Electron Devices}, number = {4}, issn = {0018-9383}, doi = {10.1109/TED.2023.3244509}, pages = {2009 -- 2014}, abstract = {Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of 8x8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices' nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems.}, language = {en} } @misc{PerezMaldonadoPerezBoschQuesadaetal., author = {Perez, Eduardo and Maldonado, David and Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Jimenez-Molinos, Francisco and Wenger, Christian}, title = {Parameter Extraction Methods for Assessing Device-to-Device and Cycle-to-Cycle Variability of Memristive Devices at Wafer Scale}, series = {IEEE Transactions on Electron Devices}, volume = {70}, journal = {IEEE Transactions on Electron Devices}, number = {1}, issn = {0018-9383}, doi = {10.1109/TED.2022.3224886}, pages = {360 -- 365}, abstract = {The stochastic nature of the resistive switching (RS) process in memristive devices makes device-to-device (DTD) and cycle-to-cycle (CTC) variabilities relevant magnitudes to be quantified and modeled. To accomplish this aim, robust and reliable parameter extraction methods must be employed. In this work, four different extraction methods were used at the production level (over all the 108 devices integrated on 200-mm wafers manufactured in the IHP 130-nm CMOS technology) in order to obtain the corresponding collection of forming, reset, and set switching voltages. The statistical analysis of the experimental data (mean and standard deviation (SD) values) was plotted by using heat maps, which provide a good summary of the whole data at a glance and, in addition, an easy manner to detect inhomogeneities in the fabrication process.}, language = {en} }