@misc{SoltaniZarrinWenger,
author = {Soltani Zarrin, Pouya and Wenger, Christian},
title = {Implementation of Siamese-Based Few-Shot Learning Algorithms for the Distinction of COPD and Asthma Subjects},
series = {Artificial Neural Networks and Machine Learning - ICANN 2020 : 29th International Conference on Artificial Neural Networks, Bratislava, Slovakia, September 15-18, 2020, Proceedings, Part I},
journal = {Artificial Neural Networks and Machine Learning - ICANN 2020 : 29th International Conference on Artificial Neural Networks, Bratislava, Slovakia, September 15-18, 2020, Proceedings, Part I},
publisher = {Springer},
address = {Cham},
doi = {10.1007/978-3-030-61609-0_34},
pages = {431 -- 440},
abstract = {This paper investigates the practicality of applying braininspired Few-Shot Learning (FSL) algorithms for addressing shortcomings of Machine Learning (ML) methods in medicine with limited data availability. As a proof of concept, the application of ML for the detection of Chronic Obstructive Pulmonary Disease (COPD) patients was investigated. The complexities associated with the distinction of COPD and asthma patients and the lack of sufficient training data for asthma subjects impair the performance of conventional ML models for the recognition of COPD. Therefore, the objective of this study was to implement FSL methods for the distinction of COPD and asthma subjects with a few available data points. The proposed FSL models in this work were capable of recognizing asthma and COPD patients with 100\% accuracy, demonstrating the feasibility of the approach for applications such as medicine with insufficient data availability.},
language = {en}
}
@misc{ZanottiPuglisiMiloetal.,
author = {Zanotti, Tommaso and Puglisi, Francesco Maria and Milo, Valerio and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Ossorio, {\´O}scar G. and Wenger, Christian and Pavan, Paolo and Olivo, Piero and Ielmini, Daniele},
title = {Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays},
series = {IEEE Transactions on Electron Devices},
volume = {67},
journal = {IEEE Transactions on Electron Devices},
number = {11},
issn = {0018-9383},
doi = {10.1109/TED.2020.3025271},
pages = {4611 -- 4615},
abstract = {Logic-in-memory (LiM) circuits based on resistive random access memory (RRAM) devices and the material implication logic are promising candidates for the development of low-power computing devices that could fulfill the growing demand of distributed computing systems. However, these circuits are affected by many reliability challenges that arise from device nonidealities (e.g., variability) and the characteristics of the employed circuit architecture. Thus, an accurate investigation of the variability at the array level is needed to evaluate the reliability and performance of such circuit architectures. In this work, we explore the reliability and performance of smart IMPLY (SIMPLY) (i.e., a recently proposed LiM architecture with improved reliability and performance) on two 4-kb RRAM arrays based on different resistive switching oxides integrated in the back end of line (BEOL) of the 0.25- μm BiCMOS process. We analyze the tradeoff between reliability and energy consumption of SIMPLY architecture by exploiting the results of an extensive array-level variability characterization of the two technologies. Finally, we study the worst case performance of a full adder implemented with the SIMPLY architecture and benchmark it on the analogous CMOS implementation.},
language = {en}
}
@misc{ZahariPerezMahadevaiahetal.,
author = {Zahari, Finn and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Kohlstedt, Hermann and Wenger, Christian and Ziegler, Martin},
title = {Analogue pattern recognition with stochastic switching binary CMOS‑integrated memristive devices},
series = {Scientific Reports},
volume = {10},
journal = {Scientific Reports},
issn = {2045-2322},
doi = {10.1038/s41598-020-71334-x},
pages = {15},
abstract = {Biological neural networks outperform todays computer technology in terms of power consumption and computing speed when associative tasks, like pattern recognition, are to be solved. The analogue and massive parallel in-memory computing in biology differs strongly with conventional transistor electronics using the von Neumann architecture. Therefore, novel bio-inspired computing architectures are recently highly investigated in the area of neuromorphic computing. Here, memristive devices, which serve as non-volatile resistive memory, are used to emulate the plastic behaviour of biological synapses. In particular, CMOS integrated resistive random access memory (RRAM) devices are promising candidates to extend conventional CMOS technology in neuromorphic systems. However, dealing with the inherent stochasticity of the resistive switching effect can be challenging for network performance. In this work, the probabilistic switching is exploited to emulate stochastic plasticity with fully CMOS integrated binary RRAM devices. Two different RRAM technologies with different device variabilities are investigated in detail and their use in a stochastic artificial neural network (StochANN) to solve the MINST pattern recognition task is examined. A mixed-signal implementation with hardware synapses and software neurons as well as numerical simulations show the proposed concept of stochastic computing is able to handle analogue data with binary memory cells.},
language = {en}
}
@misc{PetzoldPirosEilhardtetal.,
author = {Petzold, Stefan and Piros, Eszter and Eilhardt, Robert and Zintler, Alexander and Vogel, Tobias and Kaiser, Nico and Radetinac, Aldin and Komissinskiy, Philipp and Jalaguier, Eric and Nolot, Emmanuel and Charpin-Nicolle, Christelle and Wenger, Christian and Molina-Luna, Leopoldo and Miranda, Enrique and Alff, Lambert},
title = {Tailoring the Switching Dynamics in Yttrium Oxide-Based RRAM Devices by Oxygen Engineering: From Digital to Multi-Level Quantization toward Analog Switching},
series = {Advanced Electronic Materials},
volume = {6},
journal = {Advanced Electronic Materials},
number = {11},
issn = {2199-160X},
doi = {10.1002/aelm.202000439},
pages = {13},
abstract = {This work investigates the transition from digital to gradual or analog resistive switching in yttrium oxide-based resistive random-access memory devices. It is shown that this transition is determined by the amount of oxygen in the functional layer. A homogeneous reduction of the oxygen content not only reduces the electroforming voltage, allowing for forming-free devices, but also decreases the voltage operation window of switching, thereby reducing intra-device variability. The most important effect as the dielectric becomes substoichiometric by oxygen engineering is that more intermediate (quantized) conduction states are accessible. A key factor for this reproducibly controllable behavior is the reduced local heat dissipation in the filament region due to the increased thermal conductivity of the oxygen depleted layer. The improved accessibility of quantized resistance states results in a semi-gradual switching both for the set and reset processes, as strongly desired for multi-bit storage and for an accurate definition of the synaptic weights in neuromorphic systems. A theoretical model based on the physics of mesoscopic structures describing current transport through a nano-constriction including asymmetric potential drops at the electrodes and non-linear conductance quantization is provided. The results contribute to a deeper understanding on how to tailor materials properties for novel memristive functionalities.},
language = {en}
}
@misc{PerezAvilaGonzalezCorderoPerezetal.,
author = {Perez-Avila, Antonio Javier and Gonzalez-Cordero, Gerardo and P{\´e}rez, Eduardo and Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Wenger, Christian and Roldan, Juan Bautista and Jimenez-Molinos, Francisco},
title = {Behavioral modeling of multilevel HfO2-based memristors for neuromorphic circuit simulation},
series = {XXXV Conference on Design of Circuits and Integrated Systems (DCIS), Segovia, Spain},
journal = {XXXV Conference on Design of Circuits and Integrated Systems (DCIS), Segovia, Spain},
doi = {10.1109/DCIS51330.2020.9268652},
abstract = {An artificial neural network based on resistive switching memristors is implemented and simulated in LTspice. The influence of memristor variability and the reduction of the continuous range of synaptic weights into a discrete set of conductance levels is analyzed. To do so, a behavioral model is proposed for multilevel resistive switching memristors based on Al-doped HfO2 dielectrics, and it is implemented in a spice based circuit simulator. The model provides an accurate description of the conductance in the different conductive states in addition to describe the device-to-device variability},
language = {en}
}
@misc{PerezOssorioDuenasetal.,
author = {P{\´e}rez, Eduardo and Ossorio, {\´O}scar G. and Due{\~n}as, Salvador and Cast{\´a}n, Helena and Garc{\´i}a, Hector and Wenger, Christian},
title = {Programming Pulse Width Assessment for Reliable and Low-Energy Endurance Performance in Al:HfO2-Based RRAM Arrays},
series = {Electronics (MDPI)},
volume = {9},
journal = {Electronics (MDPI)},
number = {5},
issn = {2079-9292},
doi = {10.3390/electronics9050864},
abstract = {A crucial step in order to achieve fast and low-energy switching operations in resistive random access memory (RRAM) memories is the reduction of the programming pulse width. In this study, the incremental step pulse with verify algorithm (ISPVA) was implemented by using different pulse widths between 10 μ s and 50 ns and assessed on Al-doped HfO 2 4 kbit RRAM memory arrays. The switching stability was assessed by means of an endurance test of 1k cycles. Both conductive levels and voltages needed for switching showed a remarkable good behavior along 1k reset/set cycles regardless the programming pulse width implemented. Nevertheless, the distributions of voltages as well as the amount of energy required to carry out the switching operations were definitely affected by the value of the pulse width. In addition, the data retention was evaluated after the endurance analysis by annealing the RRAM devices at 150 °C along 100 h. Just an almost negligible increase on the rate of degradation of about 1 μ A at the end of the 100 h of annealing was reported between those samples programmed by employing a pulse width of 10 μ s and those employing 50 ns. Finally, an endurance performance of 200k cycles without any degradation was achieved on 128 RRAM devices by using programming pulses of 100 ns width},
language = {en}
}
@misc{MoralesMahmoodinezhadSchubertetal.,
author = {Morales, Carlos and Mahmoodinezhad, Ali and Schubert, Andreas Markus and Wenger, Christian and Henkel, Karsten and Flege, Jan Ingo},
title = {Functional ultra-thin oxide films deposited by atomic layer deposition on structured substrates},
series = {Verhandlungen der DPG - SurfaceScience21},
volume = {2021},
journal = {Verhandlungen der DPG - SurfaceScience21},
publisher = {Deutsche Physikalische Gesellschaft e.V.},
address = {Bad Honnef},
abstract = {In the last decades, atomic layer deposition (ALD) has gained prominence in the materials and surface science communities owing to its high potential for integration as a scalable process in microelectronics. ALD's largest strengths are its well-controlled layer-by-layer deposition and growth conformity on 3D structures. Yet, the ALD technique is also well known to lead to amorphous and defective, non-stoichiometric thin films, resulting in modified materials properties that may even preferentially be used in certain applications. To study these issues, we have developed an in-situ ALD reactor attached to an X-ray photoelectron spectroscopy (XPS) system, capable of switching between both pump and flow-type operation. This novel tool allows to cover the entire range of compounds and recipes used in ALD, thus clarifying the role of such defects at different deposition stages, growth conditions and film/substrate interfaces. To exemplify these sorts of studies, we show the deposition of Al2O3 5-10 nm films on nanostructured Si, and their use as substrates for functional CeOx ALD deposits.},
language = {en}
}
@misc{PerezBoschQuesadaRomeroZalizPerezetal.,
author = {P{\´e}rez-Bosch Quesada, Emilio and Romero-Zaliz, Roc{\´i}o and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Reuben, John and Schubert, Markus Andreas and Jim{\´e}nez-Molinos, Francisco and Rold{\´a}n, Juan Bautista and Wenger, Christian},
title = {Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems},
series = {Electronics (MDPI)},
volume = {10},
journal = {Electronics (MDPI)},
number = {6},
issn = {2079-9292},
doi = {10.3390/electronics10060645},
pages = {13},
abstract = {In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.},
language = {en}
}
@misc{PechmannMaiVoelkeletal.,
author = {Pechmann, Stefan and Mai, Timo and V{\"o}lkel, Matthias and Mahadevaiah, Mamathamba Kalishettyhalli and P{\´e}rez, Eduardo and Perez-Bosch Quesada, Emilio and Reichenbach, Marc and Wenger, Christian and Hagelauer, Amelie},
title = {A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells},
series = {Electronics},
volume = {10},
journal = {Electronics},
number = {5},
issn = {2079-9292},
doi = {10.3390/electronics10050530},
pages = {17},
abstract = {In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.},
language = {en}
}
@misc{MatbaechiEttehadWenger,
author = {Matbaechi Ettehad, Honeyeh and Wenger, Christian},
title = {Characterization and Separation of Live and Dead Yeast Cells Using CMOS-Based DEP Microfluidics},
series = {Micromachines},
volume = {12},
journal = {Micromachines},
number = {3},
issn = {2072-666X},
doi = {10.3390/mi12030270},
pages = {19},
abstract = {This study aims at developing a miniaturized CMOS integrated silicon-based microfluidic system, compatible with a standard CMOS process, to enable the characterization, and separation of live and dead yeast cells (as model bio-particle organisms) in a cell mixture using the DEP technique. DEP offers excellent benefits in terms of cost, operational power, and especially easy electrode integration with the CMOS architecture, and requiring label-free sample preparation. This can increase the likeliness of using DEP in practical settings. In this work the DEP force was generated using an interdigitated electrode arrays (IDEs) placed on the bottom of a CMOS-based silicon microfluidic channel. This system was primarily used for the immobilization of yeast cells using DEP. This study validated the system for cell separation applications based on the distinct responses of live and dead cells and their surrounding media. The findings confirmed the device's capability for efficient, rapid and selective cell separation. The viability of this CMOS embedded microfluidic for dielectrophoretic cell manipulation applications and compatibility of the dielectrophoretic structure with CMOS production line and electronics, enabling its future commercially mass production.},
language = {en}
}
@misc{PerezPerezAvilaRomeroZalizetal.,
author = {P{\´e}rez, Eduardo and P{\´e}rez-{\´A}vila, Antonio Javier and Romero-Zaliz, Roc{\´i}o and Mahadevaiah, Mamathamba Kalishettyhalli and P{\´e}rez-Bosch Quesada, Emilio and Roldan, Juan Bautista and Jim{\´e}nez-Molinos, Francisco and Wenger, Christian},
title = {Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing},
series = {Electronics (MDPI)},
volume = {10},
journal = {Electronics (MDPI)},
number = {9},
issn = {2079-9292},
doi = {10.3390/electronics10091084},
pages = {15},
abstract = {Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8×8 vector-matrixmultiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6\% compared with the use of non-optimized parameters.},
language = {en}
}
@misc{MiloAnzaloneZambellietal.,
author = {Milo, Valerio and Anzalone, Francesco and Zambelli, Cristian and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Ossorio, {\´O}scar G. and Olivo, Piero and Wenger, Christian and Ielmini, Daniele},
title = {Optimized programming algorithms for multilevel RRAM in hardware neural networks},
series = {IEEE International Reliability Physics Symposium (IRPS), 2021},
journal = {IEEE International Reliability Physics Symposium (IRPS), 2021},
isbn = {978-1-7281-6894-4},
issn = {1938-1891},
doi = {10.1109/IRPS46558.2021.9405119},
abstract = {A key requirement for RRAM in neural network accelerators with a large number of synaptic parameters is the multilevel programming. This is hindered by resistance imprecision due to cycle-to-cycle and device-to-device variations. Here, we compare two multilevel programming algorithms to minimize resistance variations in a 4-kbit array of HfO 2 RRAM. We show that gate-based algorithms have the highest reliability. The optimized scheme is used to implement a neural network with 9-level weights, achieving 91.5\% (vs. software 93.27\%) in MNIST recognition.},
language = {en}
}
@misc{PetrykDykaPerezetal.,
author = {Petryk, Dmytro and Dyka, Zoya and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Kabin, Ievgen and Wenger, Christian and Langend{\"o}rfer, Peter},
title = {Evaluation of the Sensitivity of RRAM Cells to Optical Fault Injection Attacks},
series = {EUROMICRO Conference on Digital System Design (DSD 2020), Special Session: Architecture and Hardware for Security Applications (AHSA)},
journal = {EUROMICRO Conference on Digital System Design (DSD 2020), Special Session: Architecture and Hardware for Security Applications (AHSA)},
isbn = {978-1-7281-9535-3},
issn = {978-1-7281-9536-0},
doi = {10.1109/DSD51259.2020.00047},
pages = {8},
language = {en}
}
@misc{RomeroZalizPerezJimenezMolinosetal.,
author = {Romero-Zaliz, Roc{\´i}o and P{\´e}rez, Eduardo and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista},
title = {Influence of variability on the performance of HfO2 memristor-based convolutional neural networks},
series = {Solid State Electronics},
volume = {185},
journal = {Solid State Electronics},
issn = {0038-1101},
doi = {10.1016/j.sse.2021.108064},
pages = {5},
abstract = {A study of convolutional neural networks (CNNs) was performed to analyze the influence of quantization and variability in the network synaptic weights. Different CNNs were considered accounting for the number of convolutional layers, size of the filters in the convolutional layer, number of neurons in the final network layers and different sets of quantization levels. The conductance levels of fabricated 1T1R structures based on HfO2 memristors were considered as reference for four or eight level quantization processes at the inference stage of the CNNs, which were previous trained with the MNIST dataset. We also included the variability of the experimental conductance levels that was found to be Gaussian distributed and was correspondingly modeled for the synaptic weight implementation.},
language = {en}
}
@misc{PerezMahadevaiahPerezBoschQuesadaetal.,
author = {P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Perez-Bosch Quesada, Emilio and Wenger, Christian},
title = {Variability and Energy Consumption Tradeoffs in Multilevel Programming of RRAM Arrays},
series = {IEEE Transactions on Electron Devices},
volume = {68},
journal = {IEEE Transactions on Electron Devices},
number = {6},
issn = {0018-9383},
doi = {10.1109/TED.2021.3072868},
pages = {2693 -- 2698},
abstract = {Achieving a reliable multi-level programming operation in resistive random access memory (RRAM) arrays is still a challenging task. In this work, we assessed the impact of the voltage step value used by the programming algorithm on the device-to-device (DTD) variability of the current distributions of four conductive levels and on the energy consumption featured by programming 4-kbit HfO2-based RRAM arrays. Two different write-verify algorithms were considered and compared, namely, the incremental gate voltage with verify algorithm (IGVVA) and the incremental step pulse with verify algorithm (ISPVA). By using the IGVVA, a main trade-off has to be taken into account since reducing the voltage step leads to a smaller DTD variability at the cost of a strong increase in the energy consumption. Although the ISPVA can not reduce the DTD variability as much as the IGVVA, its voltage step can be decreased in order to reduce the energy consumption with almost no impact on the DTD variability. Therefore, the final decision on which algorithm to employ should be based on the specific application targeted for the RRAM array.},
language = {en}
}
@misc{OssorioVinuesaGarciaetal.,
author = {Ossorio, {\´O}scar G. and Vinuesa, Guillermo and Garcia, Hector and Sahelices, Benjamin and Due{\~n}as, Salvador and Cast{\´a}n, Helena and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Wenger, Christian},
title = {Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications},
series = {ECS Transactions},
volume = {102},
journal = {ECS Transactions},
number = {2},
issn = {1938-6737},
doi = {10.1149/10202.0029ecst},
pages = {29 -- 35},
abstract = {The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.},
language = {en}
}
@misc{MahmoodinezhadMoralesNaumannetal.,
author = {Mahmoodinezhad, Ali and Morales, Carlos and Naumann, Franziska and Plate, Paul and Meyer, Robert and Janowitz, Christoph and Henkel, Karsten and Kot, Małgorzata and Z{\"o}llner, Marvin Hartwig and Wenger, Christian and Flege, Jan Ingo},
title = {Low-temperature atomic layer deposition of indium oxide thin films using trimethylindium and oxygen plasma},
series = {Journal of Vacuum Science and Technology A},
volume = {39},
journal = {Journal of Vacuum Science and Technology A},
number = {6},
issn = {0734-2101},
doi = {10.1116/6.0001375},
abstract = {Indium oxide (InxOy) thin films were deposited by plasma-enhanced atomic layer deposition (PEALD) using trimethylindium and oxygen plasma in a low-temperature range of 80-200 °C. The optical properties, chemical composition, crystallographic structure, and electrical characteristics of these layers were investigated by spectroscopic ellipsometry (SE), x-ray photoelectron spectroscopy (XPS), x-ray diffraction (XRD), as well as current-voltage and capacitance-voltage measurements. The SE results yielded a nearly constant growth rate of 0.56 {\AA} per cycle and a thickness inhomogeneity of ≤1.2\% across 4-in. substrates in the temperature range of 100-150 °C. The refractive index (at 632.8 nm) was found to be 2.07 for the films deposited at 150 °C. The PEALD-InxOy layers exhibit a direct (3.3 ± 0.2 eV) and an indirect (2.8 ± 0.1 eV) bandgap with an uptrend for both with increasing substrate temperature. Based on XPS characterization, all InxOy samples are free of carbon impurities and show a temperature-dependent off-stoichiometry indicating oxygen vacancies. XRD diffraction patterns demonstrate an onset of crystallization at 150 °C. Consistent with the optical, XPS, and XRD data, the films deposited at ≥150 °C possess higher electrical conductivity. Our findings prove that a low-temperature PEALD process of InxOy is feasible and promising for a high-quality thin-film deposition without chemical impurities on thermally fragile substrates.},
language = {en}
}
@misc{YunLeeKimetal.,
author = {Yun, Min Ju and Lee, Doowon and Kim, Sungho and Wenger, Christian and Kim, Hee-Dong},
title = {A nonlinear resistive switching behaviors of Ni/HfO2/TiN memory structures for self-rectifying resistive switching memory},
series = {Materials Characterization},
volume = {182},
journal = {Materials Characterization},
issn = {1044-5803},
doi = {10.1016/j.matchar.2021.111578},
pages = {7},
abstract = {This work reports forming free/self-rectifying resistive switching characteristics and dependency of the top electrode (TE) of a crystalline HfO2-based resistive switching memory device. In the memory cells, nonlinear bipolar resistive switching characteristics, i.e., an asymmetric current-voltage curve like the Schottky diode, was observed. In addition, the device exhibits resistive switching behaviors without forming process, which makes it possible to switch the resistance state under ultra-low current levels of <10 nA. In addition, compared to the resistive switching of the proposed resistive switching memory devices with different TEs, the VSET was decreased when using TE with lower work function, and the height read margin was obtained in the sample with the Ni TE, covering over 56 × 56 arrays. Consequently, these results indicate that the interface control resistive switching properties in memory structures having the Schottky junction warrant the realization of selector-free resistive switching memory cells in a high-density crossbar array.},
language = {en}
}
@misc{PerezBoschQuesadaPerezMahadevaiahetal.,
author = {Perez-Bosch Quesada, Emilio and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Wenger, Christian},
title = {Memristive-based in-memory computing: from device to large-scale CMOS integration},
series = {Neuromorphic Computing and Engineering},
volume = {1},
journal = {Neuromorphic Computing and Engineering},
number = {2},
issn = {2634-4386},
doi = {10.1088/2634-4386/ac2cd4},
pages = {8},
abstract = {With the rapid emergence of in-memory computing systems based on memristive technology, the integration of such memory devices in large-scale architectures is one of the main aspects to tackle. In this work we present a study of HfO2-based memristive devices for their integration in large-scale CMOS systems, namely 200 mm wafers. The DC characteristics of single metal-insulator-metal devices are analyzed taking under consideration device-to-device variabilities and switching properties. Furthermore, the distribution of the leakage current levels in the pristine state of the samples are analyzed and correlated to the amount of formingless memristors found among the measured devices. Finally, the obtained results are fitted into a physic-based compact model that enables their integration into larger-scale simulation environments.},
language = {en}
}
@misc{BaroniZambelliOlivoetal.,
author = {Baroni, Andrea and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele},
title = {Tackling the Low Conductance State Drift through Incremental Reset and Verify in RRAM Arrays},
series = {2021 IEEE International Integrated Reliability Workshop (IIRW), South Lake Tahoe, CA, USA, 10 December 2021},
journal = {2021 IEEE International Integrated Reliability Workshop (IIRW), South Lake Tahoe, CA, USA, 10 December 2021},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
isbn = {978-1-6654-1794-5},
issn = {2374-8036},
doi = {10.1109/IIRW53245.2021.9635613},
pages = {5},
abstract = {Resistive switching memory (RRAM) is a promising technology for highly efficient computing scenarios. RRAM arrays enabled the acceleration of neural networks for artificial intelligence and the creation of In-Memory Computing circuits. However, the arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation in those applications. Among those, one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are fundamental for an accurate Multi-level conductance operation. In this work, we tackle the issue by developing an Incremental Reset and Verify technique showing enhanced variability and reliability features compared with a traditional refresh-based approach.},
language = {en}
}
@misc{RomeroZalizCantudoPerezetal.,
author = {Romero-Zaliz, Rocio and Cantudo, Antonio and P{\´e}rez, Eduardo and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista},
title = {An Analysis on the Architecture and the Size of Quantized Hardware Neural Networks Based on Memristors},
series = {Electronics (MDPI)},
volume = {10},
journal = {Electronics (MDPI)},
number = {24},
issn = {2079-9292},
doi = {10.3390/electronics10243141},
abstract = {We have performed different simulation experiments in relation to hardware neural networks (NN) to analyze the role of the number of synapses for different NN architectures in the network accuracy, considering different datasets. A technology that stands upon 4-kbit 1T1R ReRAM arrays, where resistive switching devices based on HfO2 dielectrics are employed, is taken as a reference. In our study, fully dense (FdNN) and convolutional neural networks (CNN) were considered, where the NN size in terms of the number of synapses and of hidden layer neurons were varied. CNNs work better when the number of synapses to be used is limited. If quantized synaptic weights are included, we observed thatNNaccuracy decreases significantly as the number of synapses is reduced; in this respect, a trade-off between the number of synapses and the NN accuracy has to be achieved. Consequently, the CNN architecture must be carefully designed; in particular, it was noticed that different datasets need specific architectures according to their complexity to achieve good results. It was shown that due to the number of variables that can be changed in the optimization of a NN hardware implementation, a specific solution has to be worked in each case in terms of synaptic weight levels, NN architecture, etc.},
language = {en}
}
@misc{StankeWengerBieretal.,
author = {Stanke, Sandra and Wenger, Christian and Bier, Frank F. and H{\"o}lzel, Ralph},
title = {AC electrokinetic immobilization of influenza virus},
series = {Electrophoresis},
volume = {43},
journal = {Electrophoresis},
number = {12},
issn = {1522-2683},
doi = {10.1002/elps.202100324},
pages = {1309 -- 1321},
abstract = {The use of alternating current (AC) electrokinetic forces, like dielectrophoresis and AC electroosmosis, as a simple and fast method to immobilize sub-micrometer objects onto nanoelectrode arrays is presented. Due to its medical relevance, the influenza virus is chosen as a model organism. One of the outstanding features is that the immobilization of viral material to the electrodes can be achieved permanently, allowing subsequent handling independently from the electrical setup. Thus, by using merely electric fields, we demonstrate that the need of prior chemical surface modification could become obsolete. The accumulation of viral material over time is observed by fluorescence microscopy. The influences of side effects like electrothermal fluid flow, causing a fluid motion above the electrodes and causing an intensity gradient within the electrode array, are discussed. Due to the improved resolution by combining fluorescence microscopy with deconvolution, it is shown that the viral material is mainly drawn to the electrode edge and to a lesser extent to the electrode surface. Finally, areas of application for this functionalization technique are presented.},
language = {en}
}
@misc{BischoffLeisePerezBoschQuesadaetal.,
author = {Bischoff, Carl and Leise, Jakob and Perez-Bosch Quesada, Emilio and P{\´e}rez, Eduardo and Wenger, Christian and Kloes, Alexander},
title = {Implementation of device-to-device and cycle-to-cycle variability of memristive devices in circuit simulations},
series = {Solid-State Electronics},
volume = {194},
journal = {Solid-State Electronics},
issn = {0038-1101},
doi = {10.1016/j.sse.2022.108321},
pages = {4},
abstract = {We present a statistical procedure for the extraction of parameters of a compact model for memristive devices. Thereby, in a circuit simulation the typical fluctuations of the current-voltage (I-V) characteristics from device-to-device (D2D) and from cycle-to-cycle (C2C) can be emulated. The approach is based on the Stanford model whose parameters play a key role to integrating D2D and C2C dispersion. The influence of such variabilities over the model's parameters is investigated by using a fitting algorithm fed with experimental data. After this, the statistical distributions of the parameters are used in a Monte Carlo simulation to reproduce the I-V D2D and C2C dispersions which show a good agreement to the measured curves. The results allow the simulation of the on/off current variation for the design of RRAM cells or memristor-based artificial neural networks.},
language = {en}
}
@misc{MannocciBaroniMelacarneetal.,
author = {Mannocci, Piergiulio and Baroni, Andrea and Melacarne, Enrico and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele},
title = {In-Memory Principal Component Analysis by Crosspoint Array of Rresistive Switching Memory},
series = {IEEE Nanotechnology Magazine},
volume = {16},
journal = {IEEE Nanotechnology Magazine},
number = {2},
issn = {1932-4510},
doi = {10.1109/MNANO.2022.3141515},
pages = {4 -- 13},
abstract = {In Memory Computing (IMC) is one of the most promising candidates for data-intensive computing accelerators of machine learning (ML). A key ML algorithm for dimensionality reduction and classification is principal component analysis (PCA), which heavily relies on matrixvector multiplications (MVM) for which classic von Neumann architectures are not optimized. Here, we provide the experimental demonstration of a new IMCbased PCA algorithm based on power iteration and deflation executed in a 4-kbit array of resistive switching random-access memory (RRAM). The classification accuracy of the Wisconsin Breast Cancer data set reaches 95.43\%, close to floatingpoint implementation. Our simulations indicate a 250× improvement in energy efficiency compared to commercial GPUs, thus supporting IMC for energy-efficient ML in modern data-intensive computing.},
language = {en}
}
@misc{StrobelAlvaradoChavarinLeszczynskietal.,
author = {Strobel, Carsten and Alvarado Chavarin, Carlos and Leszczynski, Sebastian and Richter, Karola and Knaut, Martin and Reif, Johanna and V{\"o}lkel, Sandra and Albert, Matthias and Wenger, Christian and Bartha, Johann Wolfgang and Mikolajick, Thomas},
title = {Improved Graphene-base Heterojunction Transistor with Different Collector Semi-conductors for High-frequency Applications},
series = {Advanced Materials Letters},
volume = {13},
journal = {Advanced Materials Letters},
number = {1},
issn = {0976-3961},
doi = {10.5185/amlett.2022.011688},
abstract = {A new kind of transistor device with a graphene monolayer embedded between two n-type silicon layers is fabricated and characterized. The device is called graphene-base heterojunction transistor (GBHT). The base-voltage controls the current of the device flowing from the emitter via graphene to the collector. The transit time for electrons passing by the ultrathin graphene layer is extremely short which makes the device very promising for high frequency RF-electronics. The output current of the device is saturated and clearly modulated by the base voltage. Further, the silicon collector of the GBHT is replaced by germanium to improve the device performance. This enabled the collector current to be increased by almost three orders of magnitude. Also, the common-emitter current gain (Ic/Ib) increased from 10-3 to approximately 0.3 for the newly designed device. However, the ON-OFF ratio of the improved germanium based GBHT has so far been rather low. Further optimizations are necessary in order to fully exploit the potential of the graphene-base heterojunction transistor.},
language = {en}
}
@misc{FritscherKnoedtelMallahetal.,
author = {Fritscher, Markus and Kn{\"o}dtel, Johannes and Mallah, Maen and Pechmann, Stefan and Perez-Bosch Quesada, Emilio and Rizzi, Tommaso and Wenger, Christian and Reichenbach, Marc},
title = {Mitigating the Effects of RRAM Process Variation on the Accuracy of Artifical Neural Networks},
series = {Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2021. Lecture Notes in Computer Science},
journal = {Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2021. Lecture Notes in Computer Science},
publisher = {Springer},
isbn = {978-3-031-04579-0},
issn = {0302-9743},
doi = {10.1007/978-3-031-04580-6_27},
pages = {401 -- 417},
abstract = {Weight storage is a key challenge in the efficient implementation of artificial neural networks. Novel memory technologies such as RRAM are able to greatly improve density and introduce non-volatility and multibit capabilities to this component of ANN accelerators. The usage of RRAM in this domain comes with downsides, mainly caused by cycle-to-cycle and device-to-device variability leading to erroneous readouts, greatly affecting digital systems. ANNs have the ability to compensate for this by their inherent redundancy and usually exhibit a gradual deterioration in the accuracy of the task at hand. This means, that slight error rates can be acceptable for weight storage in an ANN accelerator. In this work we link device-to-device variability to the accuracy of an ANN for such an accelerator. From this study, we can estimate how strongly a certain net is affected by a certain device parameter variability. This methodology is then used to present three mitigation strategies and to evaluate how they affect the reaction of the network to variability: a) Dropout Layers b) Fault-Aware Training c) Redundancy. These mitigations are then evaluated by their ability to improve accuracy and to lower hardware overhead by providing data for a real-word example. We improved this network's resilience in such a way that it could tolerate double the variation in one of the device parameters (standard deviation of the oxide thickness can be 0.4 nm instead of 0.2 nm while maintaining sufficient accuracy.)},
language = {en}
}
@misc{MahadevaiahPerezLiskeretal.,
author = {Mahadevaiah, Mamathamba Kalishettyhalli and P{\´e}rez, Eduardo and Lisker, Marco and Schubert, Markus Andreas and Perez-Bosch Quesada, Emilio and Wenger, Christian and Mai, Andreas},
title = {Modulating the Filamentary-Based Resistive Switching Properties of HfO2 Memristive Devices by Adding Al2O3 Layers},
series = {Electronics : open access journal},
volume = {11},
journal = {Electronics : open access journal},
number = {10},
issn = {2079-9292},
doi = {10.3390/electronics11101540},
pages = {14},
abstract = {The resistive switching properties of HfO2 based 1T-1R memristive devices are electrically modified by adding ultra-thin layers of Al2O3 into the memristive device. Three different types of memristive stacks are fabricated in the 130 nm CMOS technology of IHP. The switching properties of the memristive devices are discussed with respect to forming voltages, low resistance state and high resistance state characteristics and their variabilities. The experimental I-V characteristics of set and reset operations are evaluated by using the quantum point contact model. The properties of the conduction filament in the on and off states of the memristive devices are discussed with respect to the model parameters obtained from the QPC fit.},
language = {en}
}
@misc{GlukhovMiloBaronietal.,
author = {Glukhov, Artem and Milo, Valerio and Baroni, Andrea and Lepri, Nicola and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele},
title = {Statistical model of program/verify algorithms in resistive-switching memories for in-memory neural network accelerators},
series = {2022 IEEE International Reliability Physics Symposium (IRPS)},
journal = {2022 IEEE International Reliability Physics Symposium (IRPS)},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
isbn = {978-1-6654-7950-9},
issn = {2473-2001},
doi = {10.1109/IRPS48227.2022.9764497},
pages = {3C.3-1 -- 3C.3-7},
abstract = {Resistive-switching random access memory (RRAM) is a promising technology for in-memory computing (IMC) to accelerate training and inference of deep neural networks (DNNs). This work presents the first physics-based statistical model describing (i) multilevel RRAM device program/verify (PV) algorithms by controlled set transition, (ii) the stochastic cycle-to-cycle (C2C) and device-to-device (D2D) variations within the array, and (iii) the impact of such imprecisions on the accuracy of DNN accelerators. The model can handle the full chain from RRAM materials/device parameters to the DNN performance, thus providing a valuable tool for device/circuit codesign of hardware DNN accelerators.},
language = {en}
}
@misc{JanowitzMahmoodinezhadKotetal.,
author = {Janowitz, Christoph and Mahmoodinezhad, Ali and Kot, Małgorzata and Morales, Carlos and Naumann, Franziska and Plate, Paul and Z{\"o}llner, Marvin Hartwig and B{\"a}rwolf, Florian and Stolarek, David and Wenger, Christian and Henkel, Karsten and Flege, Jan Ingo},
title = {Toward controlling the Al2O3/ZnO interface properties by in situ ALD preparation},
series = {Dalton Transactions},
volume = {51},
journal = {Dalton Transactions},
issn = {1477-9234},
doi = {10.1039/D1DT04008A},
pages = {9291 -- 9301},
abstract = {An Al2O3/ZnO heterojunction was grown on a Si single crystal substrate by subsequent thermal and plasma-assisted atomic layer deposition (ALD) in situ. The band offsets of the heterointerface were then studied by consecutive removal of the layers by argon sputtering, followed by in situ X-ray photoelectron spectroscopy. The valence band maximum and conduction band minimum of Al2O3 are found to be 1.1 eV below and 2.3 eV above those of ZnO, resulting in a type-I staggered heterojunction. An apparent reduction of ZnO to elemental Zn in the interface region was detected in the Zn 2p core level and Zn L3MM Auger spectra. This suggests an interface formation different from previous models. The reduction of ZnO to Zn in the interface region accompanied by the creation of oxygen vacancies in ZnO results in an upward band bending at the interface. Therefore, this study suggests that interfacial properties such as the band bending as well as the valence and conduction band offsets should be in situ controllable to a certain extent by careful selection of the process parameters.},
language = {en}
}
@misc{PerezMahadevaiahPerezBoschQuesadaetal.,
author = {P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Perez-Bosch Quesada, Emilio and Wenger, Christian},
title = {In-depth characterization of switching dynamics in amorphous HfO2 memristive arrays for the implementation of synaptic updating rules},
series = {Japanese Journal of Applied Physics},
volume = {61},
journal = {Japanese Journal of Applied Physics},
issn = {0021-4922},
doi = {10.35848/1347-4065/ac6a3b},
pages = {1 -- 7},
abstract = {Accomplishing truly analog conductance modulation in memristive arrays is crucial in order to implement the synaptic plasticity in hardware-based neuromorphic systems. In this paper, such a feature was addressed by exploiting the inherent stochasticity of switching dynamics in amorphous HfO2 technology. A thorough statistical analysis of experimental characteristics measured in 4 kbit arrays by using trains of identical depression/potentiation pulses with different voltage amplitudes and pulse widths provided the key to develop two different updating rules and to define their optimal programming parameters. The first rule is based on applying a specific number of identical pulses until the conductance value achieves the desired level. The second one utilized only one single pulse with a particular amplitude to achieve the targeted conductance level. In addition, all the results provided by the statistical analysis performed may play an important role in understanding better the switching behavior of this particular technology.},
language = {en}
}
@misc{BaroniGlukhovPerezetal.,
author = {Baroni, Andrea and Glukhov, Artem and P{\´e}rez, Eduardo and Wenger, Christian and Calore, Enrico and Schifano, Sebastiano Fabio and Olivo, Piero and Ielmini, Daniele and Zambelli, Cristian},
title = {An energy-efficient in-memory computing architecture for survival data analysis based on resistive switching memories},
series = {Frontiers in Neuroscience},
volume = {Vol. 16},
journal = {Frontiers in Neuroscience},
issn = {1662-4548},
doi = {10.3389/fnins.2022.932270},
pages = {1 -- 16},
abstract = {One of the objectives fostered in medical science is the so-called precision medicine, which requires the analysis of a large amount of survival data from patients to deeply understand treatment options. Tools like Machine Learning and Deep Neural Networks are becoming a de-facto standard. Nowadays, computing facilities based on the Von Neumann architecture are devoted to these tasks, yet rapidly hitting a bottleneck in performance and energy efficiency. The In-Memory Computing (IMC) architecture emerged as a revolutionary approach to overcome that issue. In this work, we propose an IMC architecture based on Resistive switching memory (RRAM) crossbar arrays to provide a convenient primitive for matrix-vector multiplication in a single computational step. This opens massive performance improvement in the acceleration of a neural network that is frequently used in survival analysis of biomedical records, namely the DeepSurv. We explored how the synaptic weights mapping strategy and the programming algorithms developed to counter RRAM non-idealities expose a performance/energy trade-off. Finally, we assessed the benefits of the proposed architectures with respect to a GPU-based realization of the same task, evidencing a tenfold improvement in terms of performance and three orders of magnitude with respect to energy efficiency.},
language = {en}
}
@misc{BogunPerezBoschQuesadaPerezetal.,
author = {Bogun, Nicolas and Perez-Bosch Quesada, Emilio and P{\´e}rez, Eduardo and Wenger, Christian and Kloes, Alexander and Schwarz, Mike},
title = {Analytical Calculation of Inference in Memristor-based Stochastic Artificial Neural Networks},
series = {29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES), 23-24 June 2022 , Wrocław, Poland},
journal = {29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES), 23-24 June 2022 , Wrocław, Poland},
isbn = {978-83-63578-22-0},
doi = {10.23919/MIXDES55591.2022.9838321},
pages = {83 -- 88},
abstract = {The impact of artificial intelligence on human life has increased significantly in recent years. However, as the complexity of problems rose aswell, increasing system features for such amount of data computation became troublesome due to the von Neumann's computer architecture. Neuromorphic computing aims to solve this problem by mimicking the parallel computation of a human brain. For this approach, memristive devices are used to emulate the synapses of a human brain. Yet, common simulations of hardware based networks require time consuming Monte-Carlo simulations to take into account the stochastic switching of memristive devices. This work presents an alternative concept making use of the convolution of the probability distribution functions (PDF) of memristor currents by its equivalent multiplication in Fourier domain. An artificial neural network is accordingly implemented to perform the inference stage with handwritten digits.},
language = {en}
}
@misc{LukosiusLukoseLiskeretal.,
author = {Lukosius, Mindaugas and Lukose, Rasuolė and Lisker, Marco and Luongo, G. and Elviretti, M. and Mai, Andreas and Wenger, Christian},
title = {Graphene Research in 200 mm CMOS Pilot Line},
series = {45th Jubilee International Convention on Information, Communication and Electronic Technology (MIPRO), 2022},
journal = {45th Jubilee International Convention on Information, Communication and Electronic Technology (MIPRO), 2022},
isbn = {978-953-233-103-5},
issn = {2623-8764},
doi = {10.23919/MIPRO55190.2022.9803362},
pages = {113 -- 117},
abstract = {Due to the unique electronic structures, graphene and other 2D Materials are considered as materials which can enable and extend the functionalities and performance in a large variety of applications, among them in microelectronics. At this point, the investigation and preparation of graphene devices in conditions resembling as close as possible the Si technology environment is of highest importance.Towards these goals, this paper focuses on the full spectra of graphene research aspects in 200mm pilot line. We investigated different process module developments such as CMOS compatible growth of high quality graphene on germanium and its growth mechanisms, transfer related challenges on target substrates, patterning, passivation and various concepts of contacting of graphene on a full 200 mm wafers. Finally, we fabricated proof-of-concept test structures e.g. TLM, Hall bars and capacitor structures to prove the feasibility of graphene processing in the pilot line of IHP.},
language = {en}
}
@misc{StrobelAlvaradoChavarinRichteretal.,
author = {Strobel, Carsten and Alvarado Chavarin, Carlos and Richter, Karola and Knaut, Martin and Reif, Johanna and Völkel, Sandra and Jahn, Andreas and Albert, Matthias and Wenger, Christian and Kirchner, Robert and Bartha, Johann Wolfgang and Mikolajick, Thomas},
title = {Novel Graphene Adjustable-Barrier Transistor with Ultra-High Current Gain},
series = {ACS Applied Materials \& Interfaces},
volume = {14},
journal = {ACS Applied Materials \& Interfaces},
number = {34},
issn = {1944-8244},
doi = {10.1021/acsami.2c10634},
pages = {39249 -- 39254},
abstract = {A graphene-based three terminal barristor device was proposed to overcome the low on/off ratios and insufficient current saturation of conventional graphene field effect transistors. In this study, we fabricated and analyzed a novel graphene-based transistor, which resembles the structure of the barristor but uses a different operating condition. This new device, termed graphene adjustable-barriers transistor (GABT), utilizes a semiconductor-based gate rather than a metal-insulator gate structure to modulate the device currents. The key feature of the device is the two graphene-semiconductor Schottky barriers with different heights that are controlled simultaneously by the gate voltage. Due to the asymmetry of the barriers, the drain current exceeds the gate current by several orders of magnitude. Thus, the GABT can be considered an amplifier with an alterable current gain. In this work, a silicon-graphene-germanium GABT with an ultra-high current gain (ID/IG up to 8 × 106) was fabricated, and the device functionality was demonstrated. Additionally, a capacitance model is applied to predict the theoretical device performance resulting in an on-off ratio above 106, a swing of 87 mV/dec, and a drivecurrent of about 1 × 106 A/cm2.},
language = {en}
}
@misc{BaroniGlukhovPerezetal.,
author = {Baroni, Andrea and Glukhov, Artem and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele and Olivo, Piero and Zambelli, Cristian},
title = {Low Conductance State Drift Characterization and Mitigation in Resistive Switching Memories (RRAM) for Artificial Neural Networks},
series = {IEEE Transactions on Device and Materials Reliability},
volume = {22},
journal = {IEEE Transactions on Device and Materials Reliability},
number = {3},
issn = {1530-4388},
doi = {10.1109/TDMR.2022.3182133},
pages = {340 -- 347},
abstract = {The crossbar structure of Resistive-switching random access memory (RRAM) arrays enabled the In-Memory Computing circuits paradigm, since they imply the native acceleration of a crucial operations in this scenario, namely the Matrix-Vector-Multiplication (MVM). However, RRAM arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation. A critical one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are mandatory for an accurate multi-level conductance operation. In this work, we analyze the benefits of a new programming algorithm that embodies Set and Reset switching operations to achieve better conductance control and lower variability. Data retention analysis performed with different temperatures for 168 hours evidence its superior performance with respect to standard programming approach. Finally, we explored the benefits of using our methodology at a higher abstraction level, through the simulation of an Artificial Neural Network for image recognition task (MNIST dataset). The accuracy achieved shows higher performance stability over temperature and time.},
language = {en}
}
@misc{PrueferWengerBieretal.,
author = {Pr{\"u}fer, Mareike and Wenger, Christian and Bier, Frank F. and Laux, Eva-Maria and H{\"o}lzel, Ralph},
title = {Activity of AC electrokinetically immobilized horseradish peroxidase},
series = {Electrophoresis},
volume = {43},
journal = {Electrophoresis},
number = {18-19},
issn = {1522-2683},
doi = {10.1002/elps.202200073},
pages = {1920 -- 1933},
abstract = {Dielectrophoresis(DEP) is an AC electrokinetic effect mainly used to manipulate cells.Smaller particles,like virions,antibodies,enzymes,andevendyemolecules can be immobilized by DEP as well. In principle, it was shown that enzymesare active after immobilization by DEP, but no quantification of the retainedactivity was reported so far. In this study, the activity of the enzyme horseradishperoxidase (HRP) is quantified after immobilization by DEP. For this, HRP is immobilized on regular arrays of titanium nitride ring electrodes of 500 nm diameter and 20 nm widths. The activity of HRP on the electrode chip is measured with a limit of detection of 60 fg HRP by observing the enzymatic turnover of Amplex Red and H2O2 to fluorescent resoruf in by fluorescence microscopy. The initial activity of the permanently immobilized HRP equals up to 45\% of the activity that can be expected for an ideal monolayer of HRP molecules on all electrodes of the array. Localization of the immobilizate on the electrodesis accomplished by staining with the fluorescent product of the enzyme reac-tion.The high residual activity of enzymes after AC field induced immobilization shows the method's suitability for biosensing and research applications.},
language = {en}
}
@misc{FranckDabrowskiSchubertetal.,
author = {Franck, Max and Dabrowski, Jaroslaw and Schubert, Markus Andreas and Wenger, Christian and Lukosius, Mindaugas},
title = {Towards the Growth of Hexagonal Boron Nitride on Ge(001)/Si Substrates by Chemical Vapor Deposition},
series = {Nanomaterials},
volume = {12},
journal = {Nanomaterials},
number = {19},
issn = {2079-4991},
doi = {10.3390/nano12193260},
abstract = {The growth of hexagonal boron nitride (hBN) on epitaxial Ge(001)/Si substrates via high-vacuum chemical vapor deposition from borazine is investigated for the first time in a systematic manner. The influences of the process pressure and growth temperature in the range of 10-7-10-3 mbar and 900-980 °C, respectively, are evaluated with respect to morphology, growth rate, and crystalline quality of the hBN films. At 900 °C, nanocrystalline hBN films with a lateral crystallite size of ~2-3 nm are obtained and confirmed by high-resolution transmission electron microscopy images. X-ray photoelectron spectroscopy confirms an atomic N:B ratio of 1 ± 0.1. A three-dimensional growth mode is observed by atomic force microscopy. Increasing the process pressure in the reactor mainly affects the growth rate, with only slight effects on crystalline quality and none on the principle growth mode. Growth of hBN at 980 °C increases the average crystallite size and leads to the formation of 3-10 well-oriented, vertically stacked layers of hBN on the Ge surface. Exploratory ab initio density functional theory simulations indicate that hBN edges are saturated by hydrogen, and it is proposed that partial de-saturation by H radicals produced on hot parts of the set-up is responsible for the growth},
language = {en}
}
@misc{GlukhovLepriMiloetal.,
author = {Glukhov, Artem and Lepri, Nicola and Milo, Valerio and Baroni, Andrea and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele},
title = {End-to-end modeling of variability-aware neural networks based on resistive-switching memory arrays},
series = {Proc. 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2022)},
journal = {Proc. 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2022)},
doi = {10.1109/VLSI-SoC54400.2022.9939653},
pages = {1 -- 5},
abstract = {Resistive-switching random access memory (RRAM) is a promising technology that enables advanced applications in the field of in-memory computing (IMC). By operating the memory array in the analogue domain, RRAM-based IMC architectures can dramatically improve the energy efficiency of deep neural networks (DNNs). However, achieving a high inference accuracy is challenged by significant variation of RRAM conductance levels, which can be compensated by (i) advanced programming techniques and (ii) variability-aware training (VAT) algorithms. In both cases, however, detailed knowledge and accurate physics-based statistical models of RRAM are needed to develop programming and VAT methodologies. This work presents an end-to-end approach to the development of highly-accurate IMC circuits with RRAM, encompassing the device modeling, the precise programming algorithm, and the VAT simulations to maximize the DNN classification accuracy in presence of conductance variations.},
language = {en}
}
@misc{WenBaroniPerezetal.,
author = {Wen, Jianan and Baroni, Andrea and P{\´e}rez, Eduardo and Ulbricht, Markus and Wenger, Christian and Krstic, Milos},
title = {Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages},
series = {2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)},
journal = {2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)},
isbn = {978-1-6654-5938-9},
issn = {2765-933X},
doi = {10.1109/DFT56152.2022.9962345},
pages = {1 -- 6},
abstract = {RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel states.},
language = {en}
}
@misc{PerezMaldonadoPerezBoschQuesadaetal.,
author = {P{\´e}rez, Eduardo and Maldonado, David and Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Jimenez-Molinos, Francisco and Wenger, Christian},
title = {Parameter Extraction Methods for Assessing Device-to-Device and Cycle-to-Cycle Variability of Memristive Devices at Wafer Scale},
series = {IEEE Transactions on Electron Devices},
volume = {70},
journal = {IEEE Transactions on Electron Devices},
number = {1},
issn = {0018-9383},
doi = {10.1109/TED.2022.3224886},
pages = {360 -- 365},
abstract = {The stochastic nature of the resistive switching (RS) process in memristive devices makes device-to-device (DTD) and cycle-to-cycle (CTC) variabilities relevant magnitudes to be quantified and modeled. To accomplish this aim, robust and reliable parameter extraction methods must be employed. In this work, four different extraction methods were used at the production level (over all the 108 devices integrated on 200-mm wafers manufactured in the IHP 130-nm CMOS technology) in order to obtain the corresponding collection of forming, reset, and set switching voltages. The statistical analysis of the experimental data (mean and standard deviation (SD) values) was plotted by using heat maps, which provide a good summary of the whole data at a glance and, in addition, an easy manner to detect inhomogeneities in the fabrication process.},
language = {en}
}
@misc{NitschRatzkePozarowskaetal.,
author = {Nitsch, Paul-G. and Ratzke, Markus and Pozarowska, Emilia and Flege, Jan Ingo and Alvarado Chavarin, Carlos and Wenger, Christian and Fischer, Inga Anita},
title = {Deposition of reduced ceria thin films by reactive magnetron sputtering for the development of a resistive gas sensor},
series = {Verhandlungen der DPG, Berlin 2024},
journal = {Verhandlungen der DPG, Berlin 2024},
publisher = {Deutsche Physikalische Gesellschaft},
address = {Bad Honnef},
issn = {0420-0195},
abstract = {The use of cerium oxide for hydrogen sensing is limited by the low electrical conductivity of layers deposited from a ceria target. To increase the electrical conductivity, partially reduced cerium oxide layers were obtained from a metallic cerium target by reactive magnetron sputtering. The proportions of the oxidation states Ce3+, present in reduced species, and Ce4+, present in fully oxidized species, were determined by ex-situ XPS. For electrical characterization, films were deposited on planarized tungsten finger electrodes. IV curves were measured over several days to investigate possible influences of oxygen and humidity on electrical conductivity. The morphological stability of the layers under ambient conditions was investigated by microscopical methods. The XPS results show a significant amount of Ce3+ in the layers. The electrical conductivity of as-grown samples is several orders of magnitude higher than that of samples grown from a ceria target. However, the conductivity decreases over time, indicating an oxidation of the layers. The surface morphology of the samples was found to be changing drastically within days, leading to partial delamination.},
language = {en}
}
@misc{StrobelAlvaradoChavarinKnautetal.,
author = {Strobel, Carsten and Alvarado Chavarin, Carlos and Knaut, Martin and V{\"o}lkel, Sandra and Albert, Matthias and Hiess, Andre and Max, Benjamin and Wenger, Christian and Kirchner, Robert and Mikolajick, Thomas},
title = {High Gain Graphene Based Hot Electron Transistor with Record High Saturated Output Current Density},
series = {Advanced Electronic Materials},
volume = {10},
journal = {Advanced Electronic Materials},
number = {2},
issn = {2199-160X},
doi = {10.1002/aelm.202300624},
abstract = {Hot electron transistors (HETs) represent an exciting frontier in semiconductor technology, holding the promise of high-speed and high-frequency electronics. With the exploration of two-dimensional materials such as graphene and new device architectures, HETs are poised to revolutionize the landscape of modern electronics. This study highlights a novel HET structure with a record output current density of 800 A/cm² and a high current gain α, fabricated using a scalable fabrication approach. The HET structure comprises two-dimensional hexagonal boron nitride (hBN) and graphene layers wet transferred to a germanium substrate. The combination of these materials results in exceptional performance, particularly in terms of the highly saturated output current density. The scalable fabrication scheme used to produce the HET opens up opportunities for large-scale manufacturing. This breakthrough in HET technology holds promise for advanced electronic applications, offering high current capabilities in a practical and manufacturable device.},
language = {en}
}
@misc{PechmannPerezWengeretal.,
author = {Pechmann, Stefan and P{\´e}rez, Eduardo and Wenger, Christian and Hagelauer, Amelie},
title = {A current mirror Based read circuit design with multi-level capability for resistive switching deviceb},
series = {2024 International Conference on Electronics, Information, and Communication (ICEIC)},
journal = {2024 International Conference on Electronics, Information, and Communication (ICEIC)},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
isbn = {979-8-3503-7188-8},
issn = {2767-7699},
doi = {10.1109/ICEIC61013.2024.10457188},
pages = {4},
abstract = {This paper presents a read circuit design for resistive memory cells based on current mirrors. The circuit utilizes high-precision current mirrors and reference cells to determine the state of resistive memory using comparators. It offers a high degree in adaptability in terms of both resistance range and number of levels. Special emphasis was put on device protection to prevent accidental programming of the memory during read operations. The realized circuit can resolve eight states with a resolution of up to 1 k Ω, realizing a digitization of the analog memory information. Furthermore, the integration in a complete memory macro is shown. The circuit was realized in a 130 nm-process but can easily be adapted to other processes and resistive memory technologies.},
language = {en}
}
@misc{NikiruyPerezBaronietal.,
author = {Nikiruy, Kristina and P{\´e}rez, Eduardo and Baroni, Andrea and Dorai Swamy Reddy, Keerthi and Pechmann, Stefan and Wenger, Christian and Ziegler, Martin},
title = {Blooming and pruning: learning from mistakes with memristive synapses},
series = {Scientific Reports},
volume = {14},
journal = {Scientific Reports},
number = {1},
issn = {2045-2322},
doi = {10.1038/s41598-024-57660-4},
abstract = {AbstractBlooming and pruning is one of the most important developmental mechanisms of the biological brain in the first years of life, enabling it to adapt its network structure to the demands of the environment. The mechanism is thought to be fundamental for the development of cognitive skills. Inspired by this, Chialvo and Bak proposed in 1999 a learning scheme that learns from mistakes by eliminating from the initial surplus of synaptic connections those that lead to an undesirable outcome. Here, this idea is implemented in a neuromorphic circuit scheme using CMOS integrated HfO2-based memristive devices. The implemented two-layer neural network learns in a self-organized manner without positive reinforcement and exploits the inherent variability of the memristive devices. This approach provides hardware, local, and energy-efficient learning. A combined experimental and simulation-based parameter study is presented to find the relevant system and device parameters leading to a compact and robust memristive neuromorphic circuit that can handle association tasks.},
language = {en}
}
@inproceedings{WenVargasZhuetal.,
author = {Wen, Jianan and Vargas, Fabian Luis and Zhu, Fukun and Reiser, Daniel and Baroni, Andrea and Fritscher, Markus and P{\´e}rez, Eduardo and Reichenbach, Marc and Wenger, Christian and Krstic, Milos},
title = {Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment},
series = {2024 IEEE 25th Latin American Test Symposium (LATS)},
booktitle = {2024 IEEE 25th Latin American Test Symposium (LATS)},
publisher = {IEEE},
doi = {10.1109/LATS62223.2024.10534601},
pages = {6},
abstract = {Emerging device technologies such as resistive RAM (RRAM) are increasingly recognized in enhancing system performance, particularly in applications demanding extensive vector-matrix multiplications (VMMs) with high parallelism. However, a significant limitation in current electronics design automation (EDA) tools is their lack of support for rapid prototyping, design space exploration, and the integration of inherent process-dependent device variability into system-level simulations, which is essential for assessing system reliability. To address this gap, we introduce a field-programmable gate array (FPGA) based emulation approach for RRAM crossbars featuring cycle-accurate emulations in real time without relying on complex device models. Our approach is based on pre-generated look-up tables (LUTs) to accurately represent the RRAM device behavior. To efficiently model the device variability at the system level, we propose using the multivariate kernel density estimation (KDE) method to augment the measured RRAM data. The proposed emulator allows precise latency determination for matrix mapping and computation operations. Meanwhile, by coupling with the NeuroSim framework, the corresponding energy consumption can be estimated. In addition to facilitating a range of in-depth system assessments, experimental results suggest a remarkable reduction of emulation time compared to the classic behavioral simulation.},
language = {en}
}
@misc{DoraiSwamyReddyPerezBaronietal.,
author = {Dorai Swamy Reddy, Keerthi and P{\´e}rez, Eduardo and Baroni, Andrea and Mahadevaiah, Mamathamba Kalishettyhalli and Marschmeyer, Steffen and Fraschke, Mirko and Lisker, Marco and Wenger, Christian and Mai, Andreas},
title = {Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance},
series = {The European Physical Journal B},
volume = {97},
journal = {The European Physical Journal B},
publisher = {Springer Science and Business Media LLC},
issn = {1434-6028},
doi = {10.1140/epjb/s10051-024-00821-1},
pages = {9},
abstract = {Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal-insulator-metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2 dielectric thickness from 8 nm to 5 nm. Additionally, 5\% Al-doped 4 nm HfO2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology.},
language = {en}
}
@misc{JiaPechmannMarkusetal.,
author = {Jia, Ruolan and Pechmann, Stefan and Markus, Fritscher and Wenger, Christian and Zhang, Lei and Hagelauer, Amelie},
title = {Soft-Error Analysis of RRAM 1T1R Compute-In-Memory Core for Artificial Neural Networks},
series = {2024 39th Conference on Design of Circuits and Integrated Systems (DCIS)},
journal = {2024 39th Conference on Design of Circuits and Integrated Systems (DCIS)},
publisher = {IEEE},
doi = {10.1109/DCIS62603.2024.10769203},
pages = {1 -- 5},
abstract = {This work analyses SEU-induced soft-errors in analog compute-in-memory cores using resistive random-access memory (RRAM) for artificial neural networks, where their bitcells utilize one-transistor-one-RRAM (1T1R) structure. This is modeled by combining the Stanford-PKU RRAM Model and the model of the radiation-induced photocurrent in access transistors. As results, this work derives the maximal RRAM crossbar size without occurring any logic flip and indicates the requirements for RRAM technology to achieve a SEU-resilient 1T1R compute-in memory cores.},
language = {en}
}
@misc{PerezBoschQuesadaMistroniJiaetal.,
author = {Perez-Bosch Quesada, Emilio and Mistroni, Alberto and Jia, Ruolan and Dorai Swamy Reddy, Keerthi and Reichmann, Felix and Castan, Helena and Due{\~n}as, Salvador and Wenger, Christian and Perez, Eduardo},
title = {Forming and resistive switching of HfO₂-based RRAM devices at cryogenic temperature},
series = {IEEE Electron Device Letters},
volume = {45},
journal = {IEEE Electron Device Letters},
number = {12},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
issn = {0741-3106},
doi = {10.1109/LED.2024.3485873},
pages = {2391 -- 2394},
abstract = {Reliable data storage technologies able to operate at cryogenic temperatures are critical to implement scalable quantum computers and develop deep-space exploration systems, among other applications. Their scarce availability is pushing towards the development of emerging memories that can perform such storage in a non-volatile fashion. Resistive Random-Access Memories (RRAM) have demonstrated their switching capabilities down to 4K. However, their operability at lower temperatures still remain as a challenge. In this work, we demonstrate for the first time the forming and resistive switching capabilities of CMOS-compatible RRAM devices at 1.4K. The HfO2-based devices are deployed following an array of 1-transistor-1-resistor (1T1R) cells. Their switching performance at 1.4K was also tested in the multilevel-cell (MLC) approach, storing up to 4 resistance levels per cell.},
language = {en}
}
@misc{WeisshauptSuergersBloosetal.,
author = {Weißhaupt, David and S{\"u}rgers, Christoph and Bloos, Dominik and Funk, Hannes Simon and Oehme, Michael and Fischer, Gerda and Schubert, Markus Andreas and Wenger, Christian and van Slageren, Joris and Fischer, Inga Anita and Schulze, J{\"o}rg},
title = {Lateral Mn5Ge3 spin-valve in contact with a high-mobility Ge two-dimensional hole gas},
series = {Semiconductor Science and Technology},
volume = {39},
journal = {Semiconductor Science and Technology},
number = {12},
publisher = {IOP Publishing},
issn = {0268-1242},
doi = {10.1088/1361-6641/ad8d06},
pages = {1 -- 10},
abstract = {Abstract Ge two-dimensional hole gases (2DHG) in strained modulation-doped quantum-wells represent a promising material platform for future spintronic applications due to their excellent spin transport properties and the theoretical possibility of efficient spin manipulation. Due to the continuous development of epitaxial growth recipes extreme high hole mobilities and low effective masses can be achieved, promising an efficient spin transport. Furthermore, the Ge 2DHG can be integrated in the well-established industrial complementary metal-oxide-semiconductor (CMOS) devices technology. However, efficient electrical spin injection into a Ge 2DHG—an essential prerequisite for the realization of spintronic devices—has not yet been demonstrated. In this work, we report the fabrication and low-temperature magnetoresistance (MR) measurements of a laterally structured Mn5Ge3/Ge 2DHG/ Mn5Ge3 device. The ferromagnetic Mn5Ge3 contacts are grown directly into the Ge quantum well by means of an interdiffusion process with a spacing of approximately 130 nm, forming a direct electrical contact between the ferromagnetic metal and the Ge 2DHG. Here, we report for the first time a clear MR signal for temperatures below 13 K possibly arising from successful spin injection into the high mobility Ge 2DHG. The results represent a step forward toward the realization of CMOS compatible spintronic devices based on a 2DHG.},
language = {en}
}
@misc{CapistaLukoseMajnoonetal.,
author = {Capista, Daniele and Lukose, Rasuole and Majnoon, Farnaz and Lisker, Marco and Wenger, Christian and Lukosius, Mindaugas},
title = {Optimization of the metal deposition process for the accurate estimation of Low Metal-Graphene Contact-Resistance},
series = {47th MIPRO ICT and Electronics Convention (MIPRO), 20-24 May 2024, Opatija, Croatia},
journal = {47th MIPRO ICT and Electronics Convention (MIPRO), 20-24 May 2024, Opatija, Croatia},
isbn = {979-8-3503-8250-1},
issn = {2623-8764},
doi = {10.1109/MIPRO60963.2024.10569895},
pages = {5},
language = {en}
}