@misc{SoltaniZarrinWenger, author = {Soltani Zarrin, Pouya and Wenger, Christian}, title = {Implementation of Siamese-Based Few-Shot Learning Algorithms for the Distinction of COPD and Asthma Subjects}, series = {Artificial Neural Networks and Machine Learning - ICANN 2020 : 29th International Conference on Artificial Neural Networks, Bratislava, Slovakia, September 15-18, 2020, Proceedings, Part I}, journal = {Artificial Neural Networks and Machine Learning - ICANN 2020 : 29th International Conference on Artificial Neural Networks, Bratislava, Slovakia, September 15-18, 2020, Proceedings, Part I}, publisher = {Springer}, address = {Cham}, doi = {10.1007/978-3-030-61609-0_34}, pages = {431 -- 440}, abstract = {This paper investigates the practicality of applying braininspired Few-Shot Learning (FSL) algorithms for addressing shortcomings of Machine Learning (ML) methods in medicine with limited data availability. As a proof of concept, the application of ML for the detection of Chronic Obstructive Pulmonary Disease (COPD) patients was investigated. The complexities associated with the distinction of COPD and asthma patients and the lack of sufficient training data for asthma subjects impair the performance of conventional ML models for the recognition of COPD. Therefore, the objective of this study was to implement FSL methods for the distinction of COPD and asthma subjects with a few available data points. The proposed FSL models in this work were capable of recognizing asthma and COPD patients with 100\% accuracy, demonstrating the feasibility of the approach for applications such as medicine with insufficient data availability.}, language = {en} } @misc{ZanottiPuglisiMiloetal., author = {Zanotti, Tommaso and Puglisi, Francesco Maria and Milo, Valerio and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Ossorio, {\´O}scar G. and Wenger, Christian and Pavan, Paolo and Olivo, Piero and Ielmini, Daniele}, title = {Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays}, series = {IEEE Transactions on Electron Devices}, volume = {67}, journal = {IEEE Transactions on Electron Devices}, number = {11}, issn = {0018-9383}, doi = {10.1109/TED.2020.3025271}, pages = {4611 -- 4615}, abstract = {Logic-in-memory (LiM) circuits based on resistive random access memory (RRAM) devices and the material implication logic are promising candidates for the development of low-power computing devices that could fulfill the growing demand of distributed computing systems. However, these circuits are affected by many reliability challenges that arise from device nonidealities (e.g., variability) and the characteristics of the employed circuit architecture. Thus, an accurate investigation of the variability at the array level is needed to evaluate the reliability and performance of such circuit architectures. In this work, we explore the reliability and performance of smart IMPLY (SIMPLY) (i.e., a recently proposed LiM architecture with improved reliability and performance) on two 4-kb RRAM arrays based on different resistive switching oxides integrated in the back end of line (BEOL) of the 0.25- μm BiCMOS process. We analyze the tradeoff between reliability and energy consumption of SIMPLY architecture by exploiting the results of an extensive array-level variability characterization of the two technologies. Finally, we study the worst case performance of a full adder implemented with the SIMPLY architecture and benchmark it on the analogous CMOS implementation.}, language = {en} } @misc{ZahariPerezMahadevaiahetal., author = {Zahari, Finn and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Kohlstedt, Hermann and Wenger, Christian and Ziegler, Martin}, title = {Analogue pattern recognition with stochastic switching binary CMOS‑integrated memristive devices}, series = {Scientific Reports}, volume = {10}, journal = {Scientific Reports}, issn = {2045-2322}, doi = {10.1038/s41598-020-71334-x}, pages = {15}, abstract = {Biological neural networks outperform todays computer technology in terms of power consumption and computing speed when associative tasks, like pattern recognition, are to be solved. The analogue and massive parallel in-memory computing in biology differs strongly with conventional transistor electronics using the von Neumann architecture. Therefore, novel bio-inspired computing architectures are recently highly investigated in the area of neuromorphic computing. Here, memristive devices, which serve as non-volatile resistive memory, are used to emulate the plastic behaviour of biological synapses. In particular, CMOS integrated resistive random access memory (RRAM) devices are promising candidates to extend conventional CMOS technology in neuromorphic systems. However, dealing with the inherent stochasticity of the resistive switching effect can be challenging for network performance. In this work, the probabilistic switching is exploited to emulate stochastic plasticity with fully CMOS integrated binary RRAM devices. Two different RRAM technologies with different device variabilities are investigated in detail and their use in a stochastic artificial neural network (StochANN) to solve the MINST pattern recognition task is examined. A mixed-signal implementation with hardware synapses and software neurons as well as numerical simulations show the proposed concept of stochastic computing is able to handle analogue data with binary memory cells.}, language = {en} } @misc{PetzoldPirosEilhardtetal., author = {Petzold, Stefan and Piros, Eszter and Eilhardt, Robert and Zintler, Alexander and Vogel, Tobias and Kaiser, Nico and Radetinac, Aldin and Komissinskiy, Philipp and Jalaguier, Eric and Nolot, Emmanuel and Charpin-Nicolle, Christelle and Wenger, Christian and Molina-Luna, Leopoldo and Miranda, Enrique and Alff, Lambert}, title = {Tailoring the Switching Dynamics in Yttrium Oxide-Based RRAM Devices by Oxygen Engineering: From Digital to Multi-Level Quantization toward Analog Switching}, series = {Advanced Electronic Materials}, volume = {6}, journal = {Advanced Electronic Materials}, number = {11}, issn = {2199-160X}, doi = {10.1002/aelm.202000439}, pages = {13}, abstract = {This work investigates the transition from digital to gradual or analog resistive switching in yttrium oxide-based resistive random-access memory devices. It is shown that this transition is determined by the amount of oxygen in the functional layer. A homogeneous reduction of the oxygen content not only reduces the electroforming voltage, allowing for forming-free devices, but also decreases the voltage operation window of switching, thereby reducing intra-device variability. The most important effect as the dielectric becomes substoichiometric by oxygen engineering is that more intermediate (quantized) conduction states are accessible. A key factor for this reproducibly controllable behavior is the reduced local heat dissipation in the filament region due to the increased thermal conductivity of the oxygen depleted layer. The improved accessibility of quantized resistance states results in a semi-gradual switching both for the set and reset processes, as strongly desired for multi-bit storage and for an accurate definition of the synaptic weights in neuromorphic systems. A theoretical model based on the physics of mesoscopic structures describing current transport through a nano-constriction including asymmetric potential drops at the electrodes and non-linear conductance quantization is provided. The results contribute to a deeper understanding on how to tailor materials properties for novel memristive functionalities.}, language = {en} } @misc{PerezAvilaGonzalezCorderoPerezetal., author = {Perez-Avila, Antonio Javier and Gonzalez-Cordero, Gerardo and P{\´e}rez, Eduardo and Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Wenger, Christian and Roldan, Juan Bautista and Jimenez-Molinos, Francisco}, title = {Behavioral modeling of multilevel HfO2-based memristors for neuromorphic circuit simulation}, series = {XXXV Conference on Design of Circuits and Integrated Systems (DCIS), Segovia, Spain}, journal = {XXXV Conference on Design of Circuits and Integrated Systems (DCIS), Segovia, Spain}, doi = {10.1109/DCIS51330.2020.9268652}, abstract = {An artificial neural network based on resistive switching memristors is implemented and simulated in LTspice. The influence of memristor variability and the reduction of the continuous range of synaptic weights into a discrete set of conductance levels is analyzed. To do so, a behavioral model is proposed for multilevel resistive switching memristors based on Al-doped HfO2 dielectrics, and it is implemented in a spice based circuit simulator. The model provides an accurate description of the conductance in the different conductive states in addition to describe the device-to-device variability}, language = {en} } @misc{PerezOssorioDuenasetal., author = {P{\´e}rez, Eduardo and Ossorio, {\´O}scar G. and Due{\~n}as, Salvador and Cast{\´a}n, Helena and Garc{\´i}a, Hector and Wenger, Christian}, title = {Programming Pulse Width Assessment for Reliable and Low-Energy Endurance Performance in Al:HfO2-Based RRAM Arrays}, series = {Electronics (MDPI)}, volume = {9}, journal = {Electronics (MDPI)}, number = {5}, issn = {2079-9292}, doi = {10.3390/electronics9050864}, abstract = {A crucial step in order to achieve fast and low-energy switching operations in resistive random access memory (RRAM) memories is the reduction of the programming pulse width. In this study, the incremental step pulse with verify algorithm (ISPVA) was implemented by using different pulse widths between 10 μ s and 50 ns and assessed on Al-doped HfO 2 4 kbit RRAM memory arrays. The switching stability was assessed by means of an endurance test of 1k cycles. Both conductive levels and voltages needed for switching showed a remarkable good behavior along 1k reset/set cycles regardless the programming pulse width implemented. Nevertheless, the distributions of voltages as well as the amount of energy required to carry out the switching operations were definitely affected by the value of the pulse width. In addition, the data retention was evaluated after the endurance analysis by annealing the RRAM devices at 150 °C along 100 h. Just an almost negligible increase on the rate of degradation of about 1 μ A at the end of the 100 h of annealing was reported between those samples programmed by employing a pulse width of 10 μ s and those employing 50 ns. Finally, an endurance performance of 200k cycles without any degradation was achieved on 128 RRAM devices by using programming pulses of 100 ns width}, language = {en} } @misc{MoralesMahmoodinezhadSchubertetal., author = {Morales, Carlos and Mahmoodinezhad, Ali and Schubert, Andreas Markus and Wenger, Christian and Henkel, Karsten and Flege, Jan Ingo}, title = {Functional ultra-thin oxide films deposited by atomic layer deposition on structured substrates}, series = {Verhandlungen der DPG - SurfaceScience21}, volume = {2021}, journal = {Verhandlungen der DPG - SurfaceScience21}, publisher = {Deutsche Physikalische Gesellschaft e.V.}, address = {Bad Honnef}, abstract = {In the last decades, atomic layer deposition (ALD) has gained prominence in the materials and surface science communities owing to its high potential for integration as a scalable process in microelectronics. ALD's largest strengths are its well-controlled layer-by-layer deposition and growth conformity on 3D structures. Yet, the ALD technique is also well known to lead to amorphous and defective, non-stoichiometric thin films, resulting in modified materials properties that may even preferentially be used in certain applications. To study these issues, we have developed an in-situ ALD reactor attached to an X-ray photoelectron spectroscopy (XPS) system, capable of switching between both pump and flow-type operation. This novel tool allows to cover the entire range of compounds and recipes used in ALD, thus clarifying the role of such defects at different deposition stages, growth conditions and film/substrate interfaces. To exemplify these sorts of studies, we show the deposition of Al2O3 5-10 nm films on nanostructured Si, and their use as substrates for functional CeOx ALD deposits.}, language = {en} } @misc{PerezBoschQuesadaRomeroZalizPerezetal., author = {P{\´e}rez-Bosch Quesada, Emilio and Romero-Zaliz, Roc{\´i}o and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Reuben, John and Schubert, Markus Andreas and Jim{\´e}nez-Molinos, Francisco and Rold{\´a}n, Juan Bautista and Wenger, Christian}, title = {Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems}, series = {Electronics (MDPI)}, volume = {10}, journal = {Electronics (MDPI)}, number = {6}, issn = {2079-9292}, doi = {10.3390/electronics10060645}, pages = {13}, abstract = {In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.}, language = {en} } @misc{PechmannMaiVoelkeletal., author = {Pechmann, Stefan and Mai, Timo and V{\"o}lkel, Matthias and Mahadevaiah, Mamathamba Kalishettyhalli and P{\´e}rez, Eduardo and Perez-Bosch Quesada, Emilio and Reichenbach, Marc and Wenger, Christian and Hagelauer, Amelie}, title = {A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells}, series = {Electronics}, volume = {10}, journal = {Electronics}, number = {5}, issn = {2079-9292}, doi = {10.3390/electronics10050530}, pages = {17}, abstract = {In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.}, language = {en} } @misc{MatbaechiEttehadWenger, author = {Matbaechi Ettehad, Honeyeh and Wenger, Christian}, title = {Characterization and Separation of Live and Dead Yeast Cells Using CMOS-Based DEP Microfluidics}, series = {Micromachines}, volume = {12}, journal = {Micromachines}, number = {3}, issn = {2072-666X}, doi = {10.3390/mi12030270}, pages = {19}, abstract = {This study aims at developing a miniaturized CMOS integrated silicon-based microfluidic system, compatible with a standard CMOS process, to enable the characterization, and separation of live and dead yeast cells (as model bio-particle organisms) in a cell mixture using the DEP technique. DEP offers excellent benefits in terms of cost, operational power, and especially easy electrode integration with the CMOS architecture, and requiring label-free sample preparation. This can increase the likeliness of using DEP in practical settings. In this work the DEP force was generated using an interdigitated electrode arrays (IDEs) placed on the bottom of a CMOS-based silicon microfluidic channel. This system was primarily used for the immobilization of yeast cells using DEP. This study validated the system for cell separation applications based on the distinct responses of live and dead cells and their surrounding media. The findings confirmed the device's capability for efficient, rapid and selective cell separation. The viability of this CMOS embedded microfluidic for dielectrophoretic cell manipulation applications and compatibility of the dielectrophoretic structure with CMOS production line and electronics, enabling its future commercially mass production.}, language = {en} }