@incollection{BertozziStranoLudovicietal., author = {Bertozzi, Davide and Strano, A. and Ludovici, D. and Pavlidis, V. and Angiolini, F. and Krstic, Milos}, title = {The Synchronization Challenge}, language = {en} } @misc{RizziBaroniGlukhovetal., author = {Rizzi, Tommaso and Baroni, Andrea and Glukhov, Artem and Bertozzi, Davide and Wenger, Christian and Ielmini, Daniele and Zambelli, Cristian}, title = {Process-Voltage-Temperature Variations Assessment in Energy-Aware Resistive RAM-Based FPGAs}, series = {IEEE Transactions on Device and Materials Reliability}, volume = {23}, journal = {IEEE Transactions on Device and Materials Reliability}, number = {3}, issn = {1530-4388}, doi = {10.1109/TDMR.2023.3259015}, pages = {328 -- 336}, abstract = {Resistive Random Access Memory (RRAM) technology holds promises to improve the Field Programmable Gate Array (FPGA) performance, reduce the area footprint, and dramatically lower run-time energy requirements compared to the state-of-the-art CMOS-based products. However, the integration of RRAM in FPGAs is hindered by the high programming power consumption and by non-ideal behaviors of the device due to its stochastic nature that may overshadow the benefits in normal operation mode. To cope with these challenges, optimized programming strategies have to be investigated. In this work, we explore the impact that different procedures to set the device have on the run-time performance. Process, voltage, and temperature (PVT) variations as well as time-dependent drift effect of the RRAM device are considered in the assessment of 4T1R MUX designs characteristics. The comparison with tradition CMOS implementations reveals how the choice of the target resistive state and the programming algorithm are key design aspects to reduce the run-time delay and energy metrics, while at the same time improving the robustness against the different sources of variations.}, language = {en} } @inproceedings{KrsticFanGrassetal., author = {Krstic, Milos and Fan, X. and Grass, Eckhard and Strano, A. and Bertozzi, Davide and Heer, Ch. and Sanders, B. and Benini, L. and Kakooe, M. R.}, title = {Moonrake Chip - GALS Demonstrator in 40 nm CMOS Technology}, language = {en} } @misc{ReiserReichenbachRizzietal., author = {Reiser, Daniel and Reichenbach, Marc and Rizzi, Tommaso and Baroni, Andrea and Fritscher, Markus and Wenger, Christian and Zambelli, Cristian and Bertozzi, Davide}, title = {Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations}, series = {21st IEEE Interregional NEWCAS Conference (NEWCAS), 26-28 June 2023, Edinburgh, United Kingdom}, journal = {21st IEEE Interregional NEWCAS Conference (NEWCAS), 26-28 June 2023, Edinburgh, United Kingdom}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {979-8-3503-0024-6}, doi = {10.1109/NEWCAS57931.2023}, abstract = {In-memory computing with resistive-switching random access memory (RRAM) crossbar arrays has the potential to overcome the major bottlenecks faced by digital hardware for data-heavy workloads such as deep learning. However, RRAM devices are subject to several non-idealities that result in significant inference accuracy drops compared with software baseline accuracy. A critical one is related to the drift of the conductance states appearing immediately at the end of program and verify algorithms that are mandatory for accurate multi-level conductance operation. The support of drift models in state-of-the-art simulation tools of memristive computationin-memory is currently only in the early stage, since they overlook key device- and array-level parameters affecting drift resilience such as the programming algorithm of RRAM cells, the choice of target conductance states and the weight-toconductance mapping scheme. The goal of this paper is to fully expose these parameters to RRAM crossbar designers as a multi-dimensional optimization space of drift resilience. For this purpose, a simulation framework is developed, which comes with the suitable abstractions to propagate the effects of those RRAM crossbar configuration parameters to their ultimate implications over inference performance stability.}, language = {en} }