@misc{BaroniZambelliOlivoetal., author = {Baroni, Andrea and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele}, title = {Tackling the Low Conductance State Drift through Incremental Reset and Verify in RRAM Arrays}, series = {2021 IEEE International Integrated Reliability Workshop (IIRW), South Lake Tahoe, CA, USA, 10 December 2021}, journal = {2021 IEEE International Integrated Reliability Workshop (IIRW), South Lake Tahoe, CA, USA, 10 December 2021}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {978-1-6654-1794-5}, issn = {2374-8036}, doi = {10.1109/IIRW53245.2021.9635613}, pages = {5}, abstract = {Resistive switching memory (RRAM) is a promising technology for highly efficient computing scenarios. RRAM arrays enabled the acceleration of neural networks for artificial intelligence and the creation of In-Memory Computing circuits. However, the arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation in those applications. Among those, one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are fundamental for an accurate Multi-level conductance operation. In this work, we tackle the issue by developing an Incremental Reset and Verify technique showing enhanced variability and reliability features compared with a traditional refresh-based approach.}, language = {en} } @misc{MannocciBaroniMelacarneetal., author = {Mannocci, Piergiulio and Baroni, Andrea and Melacarne, Enrico and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele}, title = {In-Memory Principal Component Analysis by Crosspoint Array of Rresistive Switching Memory}, series = {IEEE Nanotechnology Magazine}, volume = {16}, journal = {IEEE Nanotechnology Magazine}, number = {2}, issn = {1932-4510}, doi = {10.1109/MNANO.2022.3141515}, pages = {4 -- 13}, abstract = {In Memory Computing (IMC) is one of the most promising candidates for data-intensive computing accelerators of machine learning (ML). A key ML algorithm for dimensionality reduction and classification is principal component analysis (PCA), which heavily relies on matrixvector multiplications (MVM) for which classic von Neumann architectures are not optimized. Here, we provide the experimental demonstration of a new IMCbased PCA algorithm based on power iteration and deflation executed in a 4-kbit array of resistive switching random-access memory (RRAM). The classification accuracy of the Wisconsin Breast Cancer data set reaches 95.43\%, close to floatingpoint implementation. Our simulations indicate a 250× improvement in energy efficiency compared to commercial GPUs, thus supporting IMC for energy-efficient ML in modern data-intensive computing.}, language = {en} } @misc{GlukhovMiloBaronietal., author = {Glukhov, Artem and Milo, Valerio and Baroni, Andrea and Lepri, Nicola and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele}, title = {Statistical model of program/verify algorithms in resistive-switching memories for in-memory neural network accelerators}, series = {2022 IEEE International Reliability Physics Symposium (IRPS)}, journal = {2022 IEEE International Reliability Physics Symposium (IRPS)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {978-1-6654-7950-9}, issn = {2473-2001}, doi = {10.1109/IRPS48227.2022.9764497}, pages = {3C.3-1 -- 3C.3-7}, abstract = {Resistive-switching random access memory (RRAM) is a promising technology for in-memory computing (IMC) to accelerate training and inference of deep neural networks (DNNs). This work presents the first physics-based statistical model describing (i) multilevel RRAM device program/verify (PV) algorithms by controlled set transition, (ii) the stochastic cycle-to-cycle (C2C) and device-to-device (D2D) variations within the array, and (iii) the impact of such imprecisions on the accuracy of DNN accelerators. The model can handle the full chain from RRAM materials/device parameters to the DNN performance, thus providing a valuable tool for device/circuit codesign of hardware DNN accelerators.}, language = {en} } @misc{BaroniGlukhovPerezetal., author = {Baroni, Andrea and Glukhov, Artem and P{\´e}rez, Eduardo and Wenger, Christian and Calore, Enrico and Schifano, Sebastiano Fabio and Olivo, Piero and Ielmini, Daniele and Zambelli, Cristian}, title = {An energy-efficient in-memory computing architecture for survival data analysis based on resistive switching memories}, series = {Frontiers in Neuroscience}, volume = {Vol. 16}, journal = {Frontiers in Neuroscience}, issn = {1662-4548}, doi = {10.3389/fnins.2022.932270}, pages = {1 -- 16}, abstract = {One of the objectives fostered in medical science is the so-called precision medicine, which requires the analysis of a large amount of survival data from patients to deeply understand treatment options. Tools like Machine Learning and Deep Neural Networks are becoming a de-facto standard. Nowadays, computing facilities based on the Von Neumann architecture are devoted to these tasks, yet rapidly hitting a bottleneck in performance and energy efficiency. The In-Memory Computing (IMC) architecture emerged as a revolutionary approach to overcome that issue. In this work, we propose an IMC architecture based on Resistive switching memory (RRAM) crossbar arrays to provide a convenient primitive for matrix-vector multiplication in a single computational step. This opens massive performance improvement in the acceleration of a neural network that is frequently used in survival analysis of biomedical records, namely the DeepSurv. We explored how the synaptic weights mapping strategy and the programming algorithms developed to counter RRAM non-idealities expose a performance/energy trade-off. Finally, we assessed the benefits of the proposed architectures with respect to a GPU-based realization of the same task, evidencing a tenfold improvement in terms of performance and three orders of magnitude with respect to energy efficiency.}, language = {en} } @misc{BaroniGlukhovPerezetal., author = {Baroni, Andrea and Glukhov, Artem and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele and Olivo, Piero and Zambelli, Cristian}, title = {Low Conductance State Drift Characterization and Mitigation in Resistive Switching Memories (RRAM) for Artificial Neural Networks}, series = {IEEE Transactions on Device and Materials Reliability}, volume = {22}, journal = {IEEE Transactions on Device and Materials Reliability}, number = {3}, issn = {1530-4388}, doi = {10.1109/TDMR.2022.3182133}, pages = {340 -- 347}, abstract = {The crossbar structure of Resistive-switching random access memory (RRAM) arrays enabled the In-Memory Computing circuits paradigm, since they imply the native acceleration of a crucial operations in this scenario, namely the Matrix-Vector-Multiplication (MVM). However, RRAM arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation. A critical one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are mandatory for an accurate multi-level conductance operation. In this work, we analyze the benefits of a new programming algorithm that embodies Set and Reset switching operations to achieve better conductance control and lower variability. Data retention analysis performed with different temperatures for 168 hours evidence its superior performance with respect to standard programming approach. Finally, we explored the benefits of using our methodology at a higher abstraction level, through the simulation of an Artificial Neural Network for image recognition task (MNIST dataset). The accuracy achieved shows higher performance stability over temperature and time.}, language = {en} } @misc{GlukhovLepriMiloetal., author = {Glukhov, Artem and Lepri, Nicola and Milo, Valerio and Baroni, Andrea and Zambelli, Cristian and Olivo, Piero and P{\´e}rez, Eduardo and Wenger, Christian and Ielmini, Daniele}, title = {End-to-end modeling of variability-aware neural networks based on resistive-switching memory arrays}, series = {Proc. 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2022)}, journal = {Proc. 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2022)}, doi = {10.1109/VLSI-SoC54400.2022.9939653}, pages = {1 -- 5}, abstract = {Resistive-switching random access memory (RRAM) is a promising technology that enables advanced applications in the field of in-memory computing (IMC). By operating the memory array in the analogue domain, RRAM-based IMC architectures can dramatically improve the energy efficiency of deep neural networks (DNNs). However, achieving a high inference accuracy is challenged by significant variation of RRAM conductance levels, which can be compensated by (i) advanced programming techniques and (ii) variability-aware training (VAT) algorithms. In both cases, however, detailed knowledge and accurate physics-based statistical models of RRAM are needed to develop programming and VAT methodologies. This work presents an end-to-end approach to the development of highly-accurate IMC circuits with RRAM, encompassing the device modeling, the precise programming algorithm, and the VAT simulations to maximize the DNN classification accuracy in presence of conductance variations.}, language = {en} } @misc{WenBaroniPerezetal., author = {Wen, Jianan and Baroni, Andrea and P{\´e}rez, Eduardo and Ulbricht, Markus and Wenger, Christian and Krstic, Milos}, title = {Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages}, series = {2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, journal = {2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, isbn = {978-1-6654-5938-9}, issn = {2765-933X}, doi = {10.1109/DFT56152.2022.9962345}, pages = {1 -- 6}, abstract = {RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel states.}, language = {en} } @misc{NikiruyPerezBaronietal., author = {Nikiruy, Kristina and P{\´e}rez, Eduardo and Baroni, Andrea and Dorai Swamy Reddy, Keerthi and Pechmann, Stefan and Wenger, Christian and Ziegler, Martin}, title = {Blooming and pruning: learning from mistakes with memristive synapses}, series = {Scientific Reports}, volume = {14}, journal = {Scientific Reports}, number = {1}, issn = {2045-2322}, doi = {10.1038/s41598-024-57660-4}, abstract = {AbstractBlooming and pruning is one of the most important developmental mechanisms of the biological brain in the first years of life, enabling it to adapt its network structure to the demands of the environment. The mechanism is thought to be fundamental for the development of cognitive skills. Inspired by this, Chialvo and Bak proposed in 1999 a learning scheme that learns from mistakes by eliminating from the initial surplus of synaptic connections those that lead to an undesirable outcome. Here, this idea is implemented in a neuromorphic circuit scheme using CMOS integrated HfO2-based memristive devices. The implemented two-layer neural network learns in a self-organized manner without positive reinforcement and exploits the inherent variability of the memristive devices. This approach provides hardware, local, and energy-efficient learning. A combined experimental and simulation-based parameter study is presented to find the relevant system and device parameters leading to a compact and robust memristive neuromorphic circuit that can handle association tasks.}, language = {en} } @inproceedings{WenVargasZhuetal., author = {Wen, Jianan and Vargas, Fabian Luis and Zhu, Fukun and Reiser, Daniel and Baroni, Andrea and Fritscher, Markus and P{\´e}rez, Eduardo and Reichenbach, Marc and Wenger, Christian and Krstic, Milos}, title = {Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment}, series = {2024 IEEE 25th Latin American Test Symposium (LATS)}, booktitle = {2024 IEEE 25th Latin American Test Symposium (LATS)}, publisher = {IEEE}, doi = {10.1109/LATS62223.2024.10534601}, pages = {6}, abstract = {Emerging device technologies such as resistive RAM (RRAM) are increasingly recognized in enhancing system performance, particularly in applications demanding extensive vector-matrix multiplications (VMMs) with high parallelism. However, a significant limitation in current electronics design automation (EDA) tools is their lack of support for rapid prototyping, design space exploration, and the integration of inherent process-dependent device variability into system-level simulations, which is essential for assessing system reliability. To address this gap, we introduce a field-programmable gate array (FPGA) based emulation approach for RRAM crossbars featuring cycle-accurate emulations in real time without relying on complex device models. Our approach is based on pre-generated look-up tables (LUTs) to accurately represent the RRAM device behavior. To efficiently model the device variability at the system level, we propose using the multivariate kernel density estimation (KDE) method to augment the measured RRAM data. The proposed emulator allows precise latency determination for matrix mapping and computation operations. Meanwhile, by coupling with the NeuroSim framework, the corresponding energy consumption can be estimated. In addition to facilitating a range of in-depth system assessments, experimental results suggest a remarkable reduction of emulation time compared to the classic behavioral simulation.}, language = {en} } @misc{DoraiSwamyReddyPerezBaronietal., author = {Dorai Swamy Reddy, Keerthi and P{\´e}rez, Eduardo and Baroni, Andrea and Mahadevaiah, Mamathamba Kalishettyhalli and Marschmeyer, Steffen and Fraschke, Mirko and Lisker, Marco and Wenger, Christian and Mai, Andreas}, title = {Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance}, series = {The European Physical Journal B}, volume = {97}, journal = {The European Physical Journal B}, publisher = {Springer Science and Business Media LLC}, issn = {1434-6028}, doi = {10.1140/epjb/s10051-024-00821-1}, pages = {9}, abstract = {Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal-insulator-metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2 dielectric thickness from 8 nm to 5 nm. Additionally, 5\% Al-doped 4 nm HfO2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology.}, language = {en} } @misc{FritscherSinghRizzietal., author = {Fritscher, Markus and Singh, Simranjeet and Rizzi, Tommaso and Baroni, Andrea and Reiser, Daniel and Mallah, Maen and Hartmann, David and Bende, Ankit and Kempen, Tim and Uhlmann, Max and Kahmen, Gerhard and Fey, Dietmar and Rana, Vikas and Menzel, Stephan and Reichenbach, Marc and Krstic, Milos and Merchant, Farhad and Wenger, Christian}, title = {A flexible and fast digital twin for RRAM systems applied for training resilient neural networks}, series = {Scientific Reports}, volume = {14}, journal = {Scientific Reports}, number = {1}, publisher = {Springer Science and Business Media LLC}, issn = {2045-2322}, doi = {10.1038/s41598-024-73439-z}, pages = {13}, abstract = {Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the "ideal memristor" which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a "push button" modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).}, language = {en} } @misc{WenBaroniPerezetal., author = {Wen, Jianan and Baroni, Andrea and Perez, Eduardo and Uhlmann, Max and Fritscher, Markus and KrishneGowda, Karthik and Ulbricht, Markus and Wenger, Christian and Krstic, Milos}, title = {Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator}, series = {2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}, journal = {2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}, publisher = {IEEE}, isbn = {978-3-9819263-8-5}, issn = {1558-1101}, doi = {10.23919/DATE58400.2024.10546709}, pages = {1 -- 6}, abstract = {The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 \% and 18 \%, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83\% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero.}, language = {en} } @misc{MaldonadoBaroniAldanaetal., author = {Maldonado, David and Baroni, Andrea and Aldana, Samuel and Dorai Swamy Reddy, Keerthi and Pechmann, Stefan and Wenger, Christian and Rold{\´a}n, Juan Bautista and P{\´e}rez, Eduardo}, title = {Kinetic Monte Carlo simulation analysis of the conductance drift in Multilevel HfO2-based RRAM devices}, series = {Nanoscale}, volume = {16}, journal = {Nanoscale}, number = {40}, publisher = {Royal Society of Chemistry (RSC)}, issn = {2040-3364}, doi = {10.1039/d4nr02975e}, pages = {19021 -- 19033}, abstract = {The drift characteristics of valence change memory (VCM) devices have been analyzed through both experimental analysis and 3D kinetic Monte Carlo (kMC) simulations.}, language = {en} } @misc{RizziBaroniGlukhovetal., author = {Rizzi, Tommaso and Baroni, Andrea and Glukhov, Artem and Bertozzi, Davide and Wenger, Christian and Ielmini, Daniele and Zambelli, Cristian}, title = {Process-Voltage-Temperature Variations Assessment in Energy-Aware Resistive RAM-Based FPGAs}, series = {IEEE Transactions on Device and Materials Reliability}, volume = {23}, journal = {IEEE Transactions on Device and Materials Reliability}, number = {3}, issn = {1530-4388}, doi = {10.1109/TDMR.2023.3259015}, pages = {328 -- 336}, abstract = {Resistive Random Access Memory (RRAM) technology holds promises to improve the Field Programmable Gate Array (FPGA) performance, reduce the area footprint, and dramatically lower run-time energy requirements compared to the state-of-the-art CMOS-based products. However, the integration of RRAM in FPGAs is hindered by the high programming power consumption and by non-ideal behaviors of the device due to its stochastic nature that may overshadow the benefits in normal operation mode. To cope with these challenges, optimized programming strategies have to be investigated. In this work, we explore the impact that different procedures to set the device have on the run-time performance. Process, voltage, and temperature (PVT) variations as well as time-dependent drift effect of the RRAM device are considered in the assessment of 4T1R MUX designs characteristics. The comparison with tradition CMOS implementations reveals how the choice of the target resistive state and the programming algorithm are key design aspects to reduce the run-time delay and energy metrics, while at the same time improving the robustness against the different sources of variations.}, language = {en} } @misc{ReiserReichenbachRizzietal., author = {Reiser, Daniel and Reichenbach, Marc and Rizzi, Tommaso and Baroni, Andrea and Fritscher, Markus and Wenger, Christian and Zambelli, Cristian and Bertozzi, Davide}, title = {Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations}, series = {21st IEEE Interregional NEWCAS Conference (NEWCAS), 26-28 June 2023, Edinburgh, United Kingdom}, journal = {21st IEEE Interregional NEWCAS Conference (NEWCAS), 26-28 June 2023, Edinburgh, United Kingdom}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {979-8-3503-0024-6}, doi = {10.1109/NEWCAS57931.2023}, abstract = {In-memory computing with resistive-switching random access memory (RRAM) crossbar arrays has the potential to overcome the major bottlenecks faced by digital hardware for data-heavy workloads such as deep learning. However, RRAM devices are subject to several non-idealities that result in significant inference accuracy drops compared with software baseline accuracy. A critical one is related to the drift of the conductance states appearing immediately at the end of program and verify algorithms that are mandatory for accurate multi-level conductance operation. The support of drift models in state-of-the-art simulation tools of memristive computationin-memory is currently only in the early stage, since they overlook key device- and array-level parameters affecting drift resilience such as the programming algorithm of RRAM cells, the choice of target conductance states and the weight-toconductance mapping scheme. The goal of this paper is to fully expose these parameters to RRAM crossbar designers as a multi-dimensional optimization space of drift resilience. For this purpose, a simulation framework is developed, which comes with the suitable abstractions to propagate the effects of those RRAM crossbar configuration parameters to their ultimate implications over inference performance stability.}, language = {en} } @misc{WenVargasZhuetal., author = {Wen, Jianan and Vargas, Fabian Luis and Zhu, Fukun and Reiser, Daniel and Baroni, Andrea and Fritscher, Markus and Perez, Eduardo and Reichenbach, Marc and Wenger, Christian and Krstic, Milos}, title = {RRAMulator : an efficient FPGA-based emulator for RRAM crossbar with device variability and energy consumption evaluation}, series = {Microelectronics Reliability}, volume = {168}, journal = {Microelectronics Reliability}, publisher = {Elsevier BV}, address = {Amsterdam}, issn = {0026-2714}, doi = {10.1016/j.microrel.2025.115630}, pages = {1 -- 10}, abstract = {The in-memory computing (IMC) systems based on emerging technologies have gained significant attention due to their potential to enhance performance and energy efficiency by minimizing data movement between memory and processing unit, which is especially beneficial for data-intensive applications. Designing and evaluating systems utilizing emerging memory technologies, such as resistive RAM (RRAM), poses considerable challenges due to the limited support from electronics design automation (EDA) tools for rapid development and design space exploration. Additionally, incorporating technology-dependent variability into system-level simulations is critical to accurately assess the impact on system reliability and performance. To bridge this gap, we propose RRAMulator, a field-programmable gate array (FPGA) based hardware emulator for RRAM crossbar array. To avoid the complex device models capturing the nonlinear current-voltage (IV) relationships that degrade emulation speed and increase hardware utilization, we propose a device and variability modeling approach based on device measurements. We deploy look-up tables (LUTs) for device modeling and use the multivariate kernel density estimation (KDE) method to augment existing data, extending data variety and avoiding repetitive data usage. The proposed emulator achieves cycle-accurate, real-time emulations and provides information such as latency and energy consumption for matrix mapping and vector-matrix multiplications (VMMs). Experimental results show a significant reduction in emulation time compared to conventional behavioral simulations. Additionally, an RRAM-based discrete Fourier transform (DFT) accelerator is analyzed as a case study featuring a range of in-depth system assessments.}, language = {en} } @misc{UhlmannKrysikWenetal., author = {Uhlmann, Max and Krysik, Milosz and Wen, Jianan and Frohberg, Max and Baroni, Andrea and Reddy, Keerthi Dorai Swamy and P{\´e}rez, Eduardo and Ostrovskyy, Philip and Piotrowski, Krzysztof and Carta, Corrado and Wenger, Christian and Kahmen, Gerhard}, title = {A compact one-transistor-multiple-RRAM characterization platform}, series = {IEEE transactions on circuits and systems I : regular papers}, journal = {IEEE transactions on circuits and systems I : regular papers}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {1549-8328}, doi = {10.1109/TCSI.2025.3555234}, pages = {1 -- 12}, abstract = {Emerging non-volatile memories (eNVMs) such as resistive random-access memory (RRAM) offer an alternative solution compared to standard CMOS technologies for implementation of in-memory computing (IMC) units used in artificial neural network (ANN) applications. Existing measurement equipment for device characterisation and programming of such eNVMs are usually bulky and expensive. In this work, we present a compact size characterization platform for RRAM devices, including a custom programming unit IC that occupies less than 1 mm2 of silicon area. Our platform is capable of testing one-transistor-one-RRAM (1T1R) as well as one-transistor-multiple-RRAM (1TNR) cells. Thus, to the best knowledge of the authors, this is the first demonstration of an integrated programming interface for 1TNR cells. The 1T2R IMC cells were fabricated in the IHP's 130 nm BiCMOS technology and, in combination with other parts of the platform, are able to provide more synaptic weight resolution for ANN model applications while simultaneously decreasing the energy consumption by 50 \%. The platform can generate programming voltage pulses with a 3.3 mV accuracy. Using the incremental step pulse with verify algorithm (ISPVA) we achieve 5 non-overlapping resistive states per 1T1R device. Based on those 1T1R base states we measure 15 resulting state combinations in the 1T2R cells.}, language = {en} } @misc{BaroniPerezReddyetal., author = {Baroni, Andrea and P{\´e}rez, Eduardo and Reddy, Keerthi Dorai Swamy and Pechmann, Stefan and Wenger, Christian and Ielmini, Daniele and Zambelli, Cristian}, title = {Enhancing RRAM reliability : exploring the effects of Al doping on HfO2-based devices}, series = {IEEE transactions on device and materials reliability}, journal = {IEEE transactions on device and materials reliability}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {1530-4388}, doi = {10.1109/TDMR.2025.3581061}, pages = {1 -- 9}, abstract = {This study provides a comprehensive evaluation of RRAM devices based on HfO2 and Al-doped HfO2 insulators, focusing on critical performance metrics, including Forming yield, Post-Programming Stability (PPS), Fast Drift, Endurance, and Retention at elevated temperatures (125 ∘C). Aluminum doping significantly enhances device reliability and stability, improving Forming yield, reducing current drift during programming and Retention tests, and minimizing variability during Endurance cycling. While Al5\%:HfO2 achieves most of the observed benefits compared to pure HfO2, Al7\%:HfO2 offers incremental advantages for scenarios requiring extreme reliability. These findings position Al-doped HfO2 devices as a promising solution for RRAM-based systems in memory and neuromorphic computing, highlighting the potential trade-off between performance gains and increased fabrication complexity. This work underlines the importance of material engineering for optimizing RRAM devices in application-specific contexts.}, language = {en} } @misc{WenBaroniUhlmannetal., author = {Wen, Jianan and Baroni, Andrea and Uhlmann, Max and Perez, Eduardo and Wenger, Christian and Krstic, Milos}, title = {ReFFT : an energy-efficient RRAM-based FFT accelerator}, series = {IEEE transactions on computer-aided design of integrated circuits and systems}, journal = {IEEE transactions on computer-aided design of integrated circuits and systems}, publisher = {IEEE}, address = {Piscataway, NJ}, issn = {0278-0070}, doi = {10.1109/TCAD.2025.3627146}, pages = {1 -- 14}, abstract = {The fast Fourier transform (FFT) is a highly efficient algorithm for computing the discrete Fourier transform (DFT). It is widely employed in various applications, including digital communication, image processing, and signal analysis. Recently, in-memory computing architectures based on emerging technologies, such as resistive RAM (RRAM), have demonstrated promising performance with low hardware cost for data-intensive applications. However, directly mapping FFT onto RRAM crossbars is challenging because the algorithm relies on many small, sequential butterfly operations, while cross-bars are optimized for large-scale, highly parallel vector-matrix multiplications (VMMs). In this paper, we introduce ReFFT, a system architecture that reformulates FFT computations for efficient execution on RRAM crossbars. ReFFT combines the reduced computational complexity of FFT with the parallel VMM capability of RRAM. We incorporate measured device data into our framework to analyze the effect of variability and develop an adaptive mapping scheme that improves twiddle-factor programming accuracy, leading to a 9.9 dB peak signal-to-noise ratio (PSNR) improvement for a 256-point FFT. Compared with prior RRAM-based DFT designs, ReFFT achieves up to 4.6× and 19.5× higher energy efficiency for 256- and 2048-point FFTs, respectively. The system is further validated in digital communication and satellite image compression tasks.}, language = {en} } @misc{WenBaroniMistronietal., author = {Wen, Jianan and Baroni, Andrea and Mistroni, Alberto and Perez, Eduardo and Zambelli, Cristian and Wenger, Christian and Krstic, Milos and Bolzani P{\"o}hls, Leticia Maria}, title = {ReDiM : an efficient strategy for read disturb mitigation in RRAM-based accelerators}, series = {2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS)}, journal = {2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS)}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {979-8-3315-3334-2}, doi = {10.1109/IOLTS65288.2025.11117065}, pages = {1 -- 7}, abstract = {Resistive RAM (RRAM) has emerged as a promising non-volatile memory technology for implementing energy-efficient hardware accelerators within the in-memory computing (IMC) paradigm. However, due to the immature fabrication process and inherent material instabilities, frequent read operations during computations can induce read disturb effects, leading to unintended resistance drift and potential data corruption. Existing mitigation approaches primarily focus on detecting read disturb effects and triggering memory refresh operations. In this work, we propose an architecture-level solution that mitigates read disturb in RRAM-based accelerators. Our strategy employs crossbar duplication and decomposes the single high input pulse into two lower-amplitude pulses, effectively minimizing the risk of read disturb. To validate our approach, we develop a simulation framework that incorporates measurement data from characterized RRAM devices under read disturb stress conditions. Experimental results on VGG-8 with CIFAR-10 demonstrate that the proposed method significantly mitigates inference accuracy degradation caused by read disturb in RRAM-based accelerators, while incurring modest area and energy overheads of 12.32\% and 2.15\%, respectively. This work provides a practical and scalable solution for enhancing the robustness of RRAM-based accelerators in edge and high-performance computing applications.}, language = {en} }