TY - GEN A1 - Rotta, Randolf A1 - Prescher, Thomas A1 - Traue, Jana A1 - Nolte, Jörg T1 - In-Memory Communication Mechanisms for Many-Cores – Experiences with the Intel SCC T2 - TACC-Intel Highly Parallel Computing Symposium (TIHPCS), Austin/Texas, 2012 N2 - Many-core processors combine fast on-chip communication with access to large amounts of shared memory. This makes it possible to exploit the benefits of distributed as well as shared memory programming models within single parallel algorithms. While large amounts of data can be shared in the memory and caches, coordinating the activities of hundreds of cores relies on cross core communication mechanisms with ultra low latency for very small messages. In this paper we discuss two communication protocols for the Intel SCC and compare them to the MPI implementation of the SCC. Our micro-benchmark results underline that special purpose protocols for small messages make much finer levels of parallelism possible than general purpose message passing systems. Index Terms—many-core, message passing, shared memory Y1 - 2012 UR - https://opus4.kobv.de/opus4-UBICO/frontdoor/index/index/docId/8170 UR - http://www.tacc.utexas.edu/documents/13601/4234acca-2171-4465-aa48-7592d5e577f9 UR - http://www.tacc.utexas.edu/documents/13601/06d702ab-3f48-4942-9b07-2fbd880d4310 UR - http://www.tacc.utexas.edu/ti-hpcs12 ER -