TY - CONF A1 - Wen, Jianan A1 - Vargas, Fabian Luis A1 - Zhu, Fukun A1 - Reiser, Daniel A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Perez, Eduardo A1 - Reichenbach, Marc A1 - Wenger, Christian A1 - Krstic, Milos T1 - Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment T2 - 2024 IEEE 25th Latin American Test Symposium (LATS) N2 - Emerging device technologies such as resistive RAM (RRAM) are increasingly recognized in enhancing system performance, particularly in applications demanding extensive vector-matrix multiplications (VMMs) with high parallelism. However, a significant limitation in current electronics design automation (EDA) tools is their lack of support for rapid prototyping, design space exploration, and the integration of inherent process-dependent device variability into system-level simulations, which is essential for assessing system reliability. To address this gap, we introduce a field-programmable gate array (FPGA) based emulation approach for RRAM crossbars featuring cycle-accurate emulations in real time without relying on complex device models. Our approach is based on pre-generated look-up tables (LUTs) to accurately represent the RRAM device behavior. To efficiently model the device variability at the system level, we propose using the multivariate kernel density estimation (KDE) method to augment the measured RRAM data. The proposed emulator allows precise latency determination for matrix mapping and computation operations. Meanwhile, by coupling with the NeuroSim framework, the corresponding energy consumption can be estimated. In addition to facilitating a range of in-depth system assessments, experimental results suggest a remarkable reduction of emulation time compared to the classic behavioral simulation. KW - RRAM Y1 - 2024 UR - https://opus4.kobv.de/opus4-UBICO/frontdoor/index/index/docId/33667 PB - IEEE ER -