@inproceedings{NoackFochtSteinke, author = {Noack, Matthias and Focht, Erich and Steinke, Thomas}, title = {Heterogeneous Active Messages for Offloading on the NEC SX-Aurora TSUBASA}, series = {2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Heterogeneity in Computing Workshop (HCW 2019)}, booktitle = {2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Heterogeneity in Computing Workshop (HCW 2019)}, abstract = {The NEC SX-Aurora TSUBASA is a new generation of vector processing architectures that combines a standard Intel Xeon host with the newly developed NEC Vector Engine co-processor cards. One way to use these co-processors is offloading suitable parts of the program from the host to the Vector Engines. Currently, the only vendor-provided offloading solutions are the low-level Vector Engine Offloading (VEO) library, and a builtin reverse-offloading mechanism named VHcall. In this work, we extend the portable Heterogeneous Active Messages (HAM) based HAM-Offload framework with support for the NEC SX-Aurora TSUBASA. Therefore, we design, implement, and evaluate two messaging protocols aimed at minimising offloading cost. This sheds some light on how to achieve fast communication between host CPU and the Vector Engines of the NEC SX-Aurora TSUBASA. Compared with VEO, the DMA-based protocol reduces offloading overhead by a factor of 13×. The resulting framework enables users to write portable offload applications with low overhead, that do neither require a language extension like OpenMP, nor a special language like OpenCL. Existing HAM-Offload applications are now ready to run on the NEC SX-Aurora TSUBASA.}, language = {en} } @inproceedings{KnaustMayerSteinke, author = {Knaust, Marius and Mayer, Florian and Steinke, Thomas}, title = {OpenMP to FPGA Offloading Prototype Using OpenCL SDK}, series = {2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}, booktitle = {2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}, doi = {10.1109/IPDPSW.2019.00072}, pages = {387 -- 390}, abstract = {Field-programmable gate arrays (FPGAs) are of great interest for future high-performance computing and data analytics systems, since they are capable of efficient, highly-parallel data processing. Even though high-level synthesis became more popular in the last years, the effort of porting existing scientific software onto FPGAs is still considerable. We propose to use OpenMP target offloading as a solution, which we implement in a first prototype, making use of the preexisting OpenCL SDK of the FPGA vendor. Early results demonstrate the feasibility of this approach and also reveal that further optimizations will be necessary such that code can be written in an FPGA-agnostic way.}, language = {en} }