## Bitonic Sorting on Dynamically Reconfigurable Architectures

• Sorting is one of the most investigated tasks computers are used for. Up to now, not much research has been put into increasing the flexibility and performance of sorting applications by applying \emph{reconfigurable} computer systems. There are parallel sorting algorithms (\emph{sorting circuits}) which are highly suitable for VLSI hardware realization and which outperform sequential sorting methods applied on traditional software processors by far. But usually they require a large area that increases %But usually they also have a high area requirement, increasing with the number of keys to be sorted. This drawback concerns ASIC and statically reconfigurable systems. In this paper, we preseSorting is one of the most investigated tasks computers are used for. Up to now, not much research has been put into increasing the flexibility and performance of sorting applications by applying \emph{reconfigurable} computer systems. There are parallel sorting algorithms (\emph{sorting circuits}) which are highly suitable for VLSI hardware realization and which outperform sequential sorting methods applied on traditional software processors by far. But usually they require a large area that increases %But usually they also have a high area requirement, increasing with the number of keys to be sorted. This drawback concerns ASIC and statically reconfigurable systems. In this paper, we present a way to adopt the well-known Bitonic sorting method to dynamically reconfigurable systems such that this drawback is overcome. We present a detailed description of the design and actual implementation, and we present experimental results of our approach to show its benefits in performance and the trade-offs of our approach.

$Rev: 12793$