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Institute
There are many names we use to call them, like the (original) Wireless Sensor Networks, Wireless Sensor and Actuator Networks, Internet of Things, Cyber-Physical Systems, Cyber-Physical Systems of Systems, and some others. More or less visible, wireless sensor networks are already applied in many aspects of our lives and for different purposes. During the 20 years of Fachgespräch Sensornetze (FGSN) we were able to observe the process of the birth and evolution of wireless sensor networks. What do they look like now, from that time perspective? Is there still room for research andimprovements? Or are they maybe already that mature that everything has already been said? And what do they look like from the industry point of view? What is the future of sensor networks? Where are they heading? These retrospective and perspective views are the central topic of the 20th edition of the Fachgespräch Sensornetze (FGSN 2023) held on the 4th of September 2023 at Hasso-Plattner-Institut as part of the NetSys 2023 conference in Potsdam. We were happy to meet again, to discuss these subjects within the scientific community. The aim of this series of Fachgespräch is to give scientists from academia and industry the opportunity for an informal exchange of ideas and to strengthen cooperation in this multidisciplinary research area.
Programmable Logic Controllers (PLCs) are pivotal in Critical Infrastructures (CIs) and Industrial Control Systems (ICSs), governing processes in nuclear power plants, petrochemical factories, and water treatment systems. Despite their importance, PLCs are vulnerable to security threats, notably control logic injection attacks, aiming to sabotage physical processes. This thesis delves into PLC security, analyzing vulnerabilities in non-cryptographically and cryptographically protected PLCs, particularly Siemens S7-300 and S7-1500 models.
Siemens, an automation market leader, utilizes S7-300 PLCs in millions of applications, reflecting the broader ICS security landscape. The S7-1500 line claims resistance to cyberattacks, including control logic injections. The thesis evaluates authentication in non-cryptographically protected PLCs, introducing a stealthy control logic injection attack scenario using an S7-300 PLC and S7Comm protocol.
The second part explores integrity checks in cryptographically protected S7-1500 PLCs. Findings, encompassing disclosed vulnerabilities, lead to a severe control logic injection attack with a malicious interrupt block, conducted in an industrial setting using the S7-1500 and S7CommPlus protocol.
The final segment focuses on Profinet protocol security and an injection attack scenario. The study demonstrates adversaries manipulating critical data without prior knowledge, causing harm to physical processes. A real-world attack on a Profinet-based system with two S7-300 PLCs is executed.
The thesis concludes by proposing mitigation solutions, enhancing PLC and communication protocol security. This contribution elevates the security posture of millions of operating devices globally, advancing PLC security research.
This thesis deals with strategies for achieving high data throughput in wireless sensor networks that use a time division multiple access (TDMA) scheme to resolve medium access. The thesis uses a multi-sided approach that deals not only with the scheduling algorithm but also with the network layer and the interference model. The thesis proposes four solutions that significantly improve data throughput, fairness, and latency in the considered scenario.
The thesis starts with an overview of state-of-the-art medium access control (MAC) protocols, emphasizing TDMA. Based on this overview, it is concluded that not much space for improvement is left in the field of schedule calculation algorithms; many such algorithms are proposed up to date, and they can achieve schedule lengths close to the theoretical minimum. However, the research also reveals a lack of in-detail evaluation and comparison of these algorithms; this makes choosing the most suitable algorithm for a particular application hard and performance estimation inaccurate. Therefore, an extensive evaluation of state-of-the-art TDMA protocols using simulations and over 200 randomly generated networks was performed to tackle this issue. The results allow choosing an appropriate algorithm and estimating performance for each specific application.
Next, the problem of multiple packet transmissions during a single time slot is analyzed. State-of-the-art TDMA protocols assume that one packet can be transmitted in each slot and optimize the number of slots each node gets under this assumption. However, when nodes can transmit more than one packet, the performance of such a schedule is impaired. To solve this, the M-TreeMAC protocol is proposed; this protocol considers the actual number of packets transmitted in a time slot and optimizes the schedule accordingly. Furthermore, it is observed that the routing topology heavily impacts the schedule length created using this algorithm; an algorithm that optimizes the topology to result in the shortest schedule when M-TreeMAC is used is proposed, increasing benefits even further.
Finally, the accuracy of the 2-hop interference model, commonly used by state-of-the-art TDMA scheduling algorithms, is studied and simulated using a realistic radio model based on measurement results. The results show high packet loss ratios for packets traveling a large number of hops to reach the sink. The adaptive interference model is proposed to improve the 2-hop interference model. The proposed model can increase throughput significantly in networks with a height of ten or more hops.
In this work we investigated the resistance of different kP implementations based on the Montgomery ladder against horizontal, i.e. single trace, attacks. Applying statistical methods for the analysis we were able to reveal the secret value k completely. The reason causing the success of our attacks is the key-dependent addressing of the registers and other design blocks, which is an inherent feature of binary kP algorithms. This dependency was successfully exploited in the past by Itoh et al. analyzing many hundreds of kP traces, i.e. this attack is a vertical address-bit differential power analysis attack against Montgomery ladder. The vulnerability of the Montgomery ladder against horizontal address-bit attacks was detected and demonstrated during our investigations. We were able to reveal the scalar k exploiting the address-bit vulnerability in single trace attacks using not only statistical methods, but also Fourier transform, selected clustering methods as well as one of the simplest methods – the automatized simple SCA. We performed successful horizontal address-bit SCA attacks against both types of ECs, i.e. against highly regular Montgomery ladder and against a binary kP algorithm implementing atomic patterns. The success of our attacks shows that the regularity and atomicity principles are not effective against horizontal address-bit attacks. As a means for reducing the attack success, we investigated the hiding ability of the field multiplier which is usually the largest block of kP designs. We implemented our field multiplier for ECs over prime fields corresponding to the 4-segment Karatsuba multiplication formula that reduces the execution time and the energy consumption for a kP operation by about 40 % in comparison to multipliers exploiting the classical multiplication formula. However, the energy consumption per clock remained in our multiplier without significant changes, i.e. the protective hiding properties of the multiplier as a noise source were not decreased. Another advantage of our field multiplier is its inherent resistance to horizontal collision attacks, in contrast to multipliers based on the classic multiplication formula. Additionally, we proposed regular scheduling for the block addressing as an effective strategy for reducing the success of horizontal address-bit attacks. Combining this approach with the hiding features of the field multipliers can increase the resistance of the kP designs for both types of ECs against a broad spectrum of SCA attacks. The mentioned analysis methods can be successfully applied for determining SCA leakage sources in the early design phase.
Die zunehmende Digitalisierung unserer Gesellschaft erfordert fortwährenden Schutz von kritischen Informationen mittels kryptographischer Systeme. Algorithmisch sind diese Systeme kaum anzugreifen. Allerdings ermöglichen sogenannte Seitenkanalattacken die Extraktion von geheimen Daten. Eine Art Seitenkanalattacken mit großem Angriffspotential ist die lokalisierte elektromagnetische Analyse. Bei diesem Verfahren werden durch Messung und Analyse der elektromagnetischen Abstrahlung von Teilen der Schaltung Rückschlüsse auf interne Zustände getroffen und dadurch geheime Informationen wie private Schlüssel extrahiert. Der aktuelle Stand der Forschung im Bereich lokalisierter EMA zeigt sowohl erfolgreiche Angriffe als auch Gegenmaßnahmen auf. Jedoch werden in den veröffentlichten Arbeiten keine detaillierten Untersuchungen hinsichtlich der genauen Umsetzung des Layouts der FPGA Implementierungen untersucht, welches die Ursache für den lokalisierten Leakage bildet. Stattdessen werden die Ursachen auf der algorithmischen Ebene des verwendeten kryptographischen Verfahrens betrachtet und ebenfalls eine algorithmische Gegenmaßnahme vorgeschlagen.
In dieser Arbeit wird der Einfluss des Layouts von FPGA und ASIC Implementierungen auf lokalisierte EMA Angriffe untersucht. Dabei spielt insbesondere die Platzierung der Register eine wichtige Rolle. Die Untersuchungen in dieser Arbeit werden genutzt, um weiterführende Maßnahmen zum Schutz von kryptographischen Implementierungen planen zu können.
Die Untersuchungsergebnisse zeigen, dass sowohl das Design selbst als auch die Implementierung als FPGA oder ASIC einen großen Einfluss auf die Angreifbarkeit der Implementierung durch eine lokalisierte EMA haben. So kann die FPGA Implementierung des betrachteten ECC Designs ebenfalls für diese Art von Angriffen verwundbar sein. Aufgrund ihrer Implementierung ist dieser ECC-Beschleuniger insgesamt weniger anfällig als ein Vergleichsdesign aus dem Stand der Forschung. Dennoch konnten potentielle Schwachstellen identifiziert werden, welche die Grundlage für die Planung und Umsetzung von Gegenmaßnahmen darstellen. Bei einer FPGA Implementierung des ECC Beschleunigers ist hauptsächlich die Lage der Flip-Flops im Layout die Ursache für die Anfälligkeit. Dem kann durch eine gleichmäßige Verteilung der Register zusammen mit permanent aktiver Logik entgegengewirkt werden, da die EM Abstrahlung der Logik die der Register überdeckt. Im Gegensatz dazu konnte bei der ASIC Implementierung keine Aussage über den Einfluss von Platzierungsvarianten getroffen werden, da die Einflüsse nicht messbar waren. Allerdings konnte die Verdrahtung auf der obersten Metallschicht als Leakagequelle bestimmt werden. Als Gegenmaßnahme dazu wird vorgeschlagen, durch Constraints die Ausgangssignale von Registern eines kryptographischen Chips nicht bis in die oberste Schicht zu routen.