Refine
Document Type
- Doctoral thesis (23) (remove)
Has Fulltext
- yes (23)
Is part of the Bibliography
- no (23)
Year of publication
Language
- English (23) (remove)
Keywords
- Drahtloses Sensorsystem (4)
- Drahtlose Sensornetze (3)
- Drahtloses lokales Netz (3)
- OFDM (3)
- Eingebettetes System (2)
- Fehlererkennung (2)
- Fehlertoleranz (2)
- GALS (2)
- Security (2)
- SiGe (2)
Institute
- FG Systeme (23) (remove)
Wireless communication has become an indispensable part of our life and the demand for achieving higher throughput with lower energy consumption is ever growing. The ambitious throughput of 100 Gb/s and beyond is now becoming a modest goal thanks to comprehensive advances in transmission technologies and protocols. One important aspect of these advances is with regard to channel coding methods and the ability to detect and correct errors at the receiver. Computations needed by such methods become generally more complicated as they become more powerful in their performance. This imposes a great challenge for researchers attempting to devise practical methods for encoding and decoding Forward-error Correction (FEC) techniques tailored for high-throughput scenarios.
In this work we focus on high-throughput Quasi-Cyclic LDPC (QC-LDPC) codes, as they have been selected as one of the main FEC techniques for the two major next generation wireless technologies, namely Wi-Fi 6 (IEEE 802.11ax) and 5G. Our target is to develop complete encoding and decoding design for these codes in order to reach the throughput of 100 Gb/s with affordable power consumption. Toward this goal, we investigate first the appropriate encoder design for these codes which can be used at such high data-rate with reasonably low power consumption. Then we propose several novel ideas for improving the decoding performance and complexity of QC-LDPC codes. The proposed novel ideas collectively facilitate a decoder able to run at 50 Gb/s with less than 12 pJ/b energy consumption for a Latin squares QC-LDPC code. All the proposed methods are practical and implementable and their effectiveness are showcased by either Field Programmable Gate Array (FPGA) or Application-Specific Integrated Circuit (ASIC) synthesis.
Mixed signal integrated circuits (MSICs) contain both analog and digital circuitry, integrated together on the same die. While this integration brings many benefits, it also gives rise to the issue of substrate noise coupling between the noisy digital circuitry and noise-sensitive analog circuitry. In order to counteract this issue, various substrate noise reduction methodologies had been developed so far. This thesis explores a new approach in substrate noise reduction – using a GALS (globally-synchronous, locally-asynchronous) design strategy for the digital part of a MSIC, in order to reduce the noise generation at its source. GALS architectures consist of several locally synchronous modules (LSMs) which communicate asynchronously to each other. By converting an initially synchronous architecture of digital circuitry into a GALS architecture, simultaneous switching noise generated by this circuitry can be reduced. While GALS had already been used for reducing other types of simultaneous switching noise, this is, to the best of the author’s knowledge, the first attempt to develop a GALS-based methodology for substrate noise reduction. In order to be able to theoretically analyze GALS-based methodologies for substrate noise suppression, corresponding models at high abstraction level for substrate noise generation and substrate noise propagation in lightly doped substrates (which is a type of substrate mostly used for MSICs) have been developed. These models have further been used for developing two new GALS-based substrate noise reduction methodologies: harmonic-balanced plesiochronous GALS partitioning (HB) and harmonic-and-area-based plesiochronous GALS partitioning with power domain separation (HAB). A theoretical analysis has shown that HB can reach substrate noise attenuation of up to 20log(M), where M is the number of LSMs of the resulting GALS system. On the other hand, the attenuation achievable by HAB depends on the distribution of switching current harmonics and area among the partitions, as well as from the substrate itself. For each of the two methodologies, a suitable partitioning procedure for a practical application has been developed; these partitionig procedures have been numerically evaluated in MATLAB. HB has further been embedded within the EMIAS CAD tool, where it has been evaluated on a real design example – a wireless sensor node. A special case of HAB for low frequencies has been applied for developing a test chip called SGE (power domain Separation and Galsification Experiment). The measurements on silicon have proved the applicability of the methodology.
Factory automation applications require a communication system that concurrently supports them with determinism, reliability, short communication cycles, and precise synchronization as well as mobility and extensibility. However, neither currently employed wired nor available wireless communication networks support all of these requirements at once. On the one hand, wired networks lack mobility and extensibility. On the other hand, wireless networks do not support reliability or determinism due to the stochastic nature of wireless channels. Moreover, none of the available wireless networks enable transmission latencies of 1 ms and below. Therefore, they cannot support the required short communication cycles. However, various research initiatives and the currently developed 5G standard promise to overcome these limitations at least partially.
Nevertheless, even a corresponding wireless network will not directly replace all wired connections, but will initially be used for subsections of the data transmission, where e.g. mobility is of utmost importance. Accordingly, cascaded communication networks consisting of hierarchically ordered, wired and wireless subnetworks will emerge. In this thesis, we investigate effects and dependencies of such a cascading for the real-time communication of factory automation applications. Therefore, we have to find methods to interconnect arbitrary wired and wireless communication networks such that we can maintain the reliable real-time performance of wired subnetworks and the mobility of wireless subnetworks without, or at most with minimal performance degradation. Ideally, with a cascaded network, no hardware or software adjustments will be necessary compared to the individual networks deployed today.
Based on a delimiting review of different application areas and a dedicated use case analysis of typical factory automation applications, we derive the most challenging requirements that have to be fulfilled by cascaded communication networks. According to this review, we present several methods to reduce the overall transmission latency in cascaded networks. Starting with analyzing different interface concepts and continuing with frame conversion methods, we achieve a decision-making basis to select dedicated subnetworks for a cascaded network that can be used for closed-loop control applications. Additionally, we develop methods to optimize the parametrization of individual subnetworks with respect to the overall communication, such that the end-to-end transmission latency can be drastically reduced. For verification, we design a generic model for analyzing the timing behavior of arbitrary communication networks and verify it based on an analysis of a machine tool application scenario. Additional measurements based on a real demonstrator implementation corroborate that, in industrial application, cascaded communication networks can provide competitive performance compared to the currently used wired networks.
The requirement for wireless communication with a speed beyond 100 Gbps is growing. There are mainly two possible approaches to achieve 100 Gbps system. One approach is to target lower transmission bandwidth and very high spectral efficiency. This method requires advanced digital signal processing operations, which are power-hungry. Another possible path is to go for a high-transmission bandwidth and a moderate spectral efficiency. We decided for this direction to implement a 100 Gbps system. We have chosen parallel sequence spread spectrum (PSSS) as an analog-friendly mixed-signal modulation where most of the baseband processing is in the analog domain, and only a small part is in the digital domain. For the channel equalization, we consider an “effective channel” that takes into account the wireless channel and the effects of the transmitter and receiver hardware impairments. The influence of the nonlinear channel response was analyzed for a PSSS modulated signal by employing the RAPP model for the power amplifier. For the first time, we performed a Hardware-In-The-loop experiment using PSSS modulation in the terahertz band. A PSSS modulated signal at a chip rate of 20 Gcps with spectral efficiency of 4 bit/s/Hz is transmitted using a 230 GHz RF-frontend operating in the linear range to achieve a data rate of 80 Gbps. One more important property is that the channel estimation and equalization are performed in the analog domain. A high-speed channel equalization algorithm was developed and implemented on FPGA/ASIC, which operates at(1/10)th of PSSS symbol rate. A parallel PSSS encoder transmitter architecture was designed to work at a high chip rate, and it was implemented on FPGA /ASIC and had an energy efficiency of 0.21 pJ bit−1 on 28nm ASIC.
In this Thesis, we put forward a case for the analog-friendly modulation scheme called PSSS. This scheme does not only modulates the signal but rather builds up an eco-system (such as channel estimation, equalization, and synchronization), which is responsible for the baseband operation.
The design of 100 Gbps wireless networks is a challenging task. A serial Reed-Solomon decoder at the targeted data rate has to operate at ultra-fast clock frequency of 12.5 GHz to fulfill timing constraints of the transmission. Receiving a single Ethernet frame on the physical layer may be faster than accessing DDR3 memory. Moreover, data link layer of wireless systems has to cope with high bit error rate (BER). The BER in wireless communication can be several orders of magnitude higher than in wired systems. For example, the IEEE 802.3ba standard for 100 Gbps Ethernet limits the BER to 1e-12 at the data link layer. On the contrary, the BER of high-speed wireless RF-frontend working in the Terahertz band might be higher than 1e-3. Performing forward error correction on the state of the art FPGA (field programmable gate arrays) and ASICs requires a highly parallelized approach. Thus, new processing concepts have to be developed for fast wireless communication. Due to the mentioned factors, the data link layer for the wireless 100G communication has to be considered as new research, and cannot be adopted from other systems.
This work provides a detailed case study about 100 Gbps data link layer design with the main focus on communication reliability improvements for ultra-high-speed wireless communication. Firstly, constraints of available hardware platforms are identified (memory capacity, memory access time, and logic area). Later, simulation of popular techniques used for data link layer optimizations are presented (frame fragmentation, frames aggregation, forward error correction, acknowledge frame compression, hybrid automatic repeat request, link adaptation, selective fragment retransmission). After that, data link layer FPGA accelerator processing ~116 Gbps of user data is presented. At the end, ASIC synthesis is considered and detailed statistics of consumed energy per bit are introduced. The research includes link adaptation techniques, which optimize goodput and consumed energy according to the channel BER. To the author’s best knowledge, it is the first published data link layer implementation dedicated for 100 Gbps wireless communication shown anywhere in the world.
Conventional semiconductor memories are facing many challenges concerning their yield, reliability, testability, and manufacturability as the feature size decreases. Although they are used in the vast majority of electronic devices, their applicability for upcoming digital systems is questionable. On the other hand, due to unprecedented development of mobile devices even faster, denser, and more power-efficient semiconductor memories are required. As a consequence, many researchers and system designers are seeking new memory solutions. The greatest attention is paid to solid-state, non-volatile memories (NVMs) such as PCRAMs, MRAMs/STT-MRAMs, FeRAMs, and RRAMs. Due to their promising features like non-volatility, low-power consumption, and great scalability they are expected to meet the challenging demands of future digital systems.
Unfortunately, despite all advantages they offer, emerging NVMs pose some peculiar characteristics like limited endurance, variable data retention time, or vulnerability to external factors. On top of that, they are still in early-maturity state where their fabrication processes are not of high quality and are prone to high variations. Because of that, emerging NVMs may suffer from permanent faults which can occur right after production or in the field, during their operational time. As a consequence, the reliability of new memory technologies requires special management and great improvement.
The thesis introduces system-level approach aimed at comprehensive reliability management of existing and emerging NVMs. It presents novel on-line repair techniques which focus on specific issues of NVMs. The block-level repair manages post-production faults in the memory array. The word-level repair aims at hard faults caused by wear-out memory cells. Finally, the error-correcting code with increased hard-error correction capability handles soft and hard errors in the memory array.
Because proposed techniques are based on similar principles, they can be combined into a consistent system. Depending on the way how they are connected, different repair schemes can be achieved. Moreover, by merging them into the system a synergistic effect can be produced where the achieved memory reliability improvement is greater than the sum of reliability improvements achieved with their standalone implementations.
Further in the thesis, such a consistent repair system is presented. Next, its effectiveness, repair capabilities, and applicability for an embedded system are evaluated. In addition, the achieved synergistic effect is described and quantified
The design of embedded sensor node hardware systems is a challenging task driven by the increasing demands for low power, high efficiency, low cost and small size. These unique requirements make the usage of off-the-shelf general purpose microcontrollers fairly inefficient. For many wireless sensor network applications, the design of a dedicated low power sensor node microcontroller is the only way to answer specific application requirements. According to the trends in device, process and design technology, the development of sensor node devices is relying on a cheap planar bulk-CMOS technology, where power consumption is dominated by static power loss caused by high leakage currents. To keep the power at acceptable level, designers are compelled to apply the methodologies based on advanced low power techniques that target both static and dynamic power in the chip. The decisions made early in design phase are likely to determine the energy efficiency of the final design. Therefore, the choice of power saving strategy is the key challenge in designing energy-efficient sensor node hardware.
This work presents a methodology that assists designers meeting the critical design decisions regarding power, early in the design process. The presented methodology extracts the activity profiles of single system components and applies them in the developed models for energy estimation of particular low power implementation. The energy estimation models account for the energy overhead introduced by specific low power techniques, enabling comprehensive exploration of system’s energy efficiency in a given application scenario. Special attention is paid to the methodology utilization in typical wireless sensor network applications. Accordingly, the examples of activity profiling in wireless sensor node systems are presented. The proposed methodology is integrated within a power-driven design flow and applied to the design of an embedded sensor node microcontroller. This methodology is used to perform the cross comparison of alternative low power implementations for the target system architecture. The implementation relying on concurrent clock and power gating is selected as the most energy efficient and consequently realised. Power switching cells and power control logic have been designed and characterized. Also, the final system architecture, basic system components and applied design process are described. Finally, the developed power-gated sensor node microcontroller is implemented, fabricated and successfully tested. The chip measurements results are presented and analyzed.
The analysis of different low power approaches applied to the target system architecture has shown large impact of clock gating on the system energy. In a given application scenario, the clock gating implementation has reduced 72 times the dynamic energy and 12 times the total energy of the system. The implementation of power gating technique has gained 2.8 times reduction of the leakage energy and 2 times reduction of the total system energy compared to the clock gating only implementation. The analysis of two alternative power gating approaches has emphasized the significance of partitioning in power-gated design. A heuristic partitioning that combines two specific blocks having successive activity phases into a single power domain, thereby reducing design complexity and chip area, has been shown to have positive impact on the energy efficiency of the target design.
Despite the numerous benefits that Integrated Circuit (IC) technology downscaling brings, it also introduces many challenges. First of all, IC dependability is lowering: both lifetime reliability and resilience to single event effects is decreasing. Another major problem is the increased power consumption. On the other hand, the vast available space enables integrating hundreds of processor cores in a single chip! Multiprocessing is for over a decade the main architectural trend because of two reasons. Firstly, the performance of single processors gained by architectural innovations reached the upper limit i.e., the point of diminishing returns. Secondly, the operating frequency could not be increased due to the excessive power consumption, as pointed out. This work proposes a multiprocessor architectural framework that addresses many challenges related to dependability, power consumption and performance. The key idea is dynamical adaptation to the application requirements of fault tolerance and performance, which is possibly done at the lowest rates of aging and power dissipation. The application may select one of the three basic operating modes: de-stress, fault-tolerant and high-performance. De-stress mode prolongs multiprocessor lifetime and reduces power consumption by using core gating patterns that systematically power- or clock-off entire cores in the multiprocessor. These patterns use the information supplied by novel IC aging monitors. Fault-tolerant mode, on the other hand, increases error resilience by forming core-level NMR (N-modular redundant) systems using the multiprocessor cores. That is, entire cores are tightly synchronized to execute the same task simultaneously. Voting is done on each clock cycle using special, programmable NMR voters. Core-level NMR enables masking faults without invoking recovery procedures which is appreciated by timing-critical, or, real-time applications. Finally, high-performance mode is used for boosting multiprocessor performance. The framework is evaluated using a novel environment for automated fault injection, as well as a novel multiprocessor verification platform. A vast number of experiments were made which led to closed-form expressions that determine the number of cores N required to survive the projected mission time, given the fault rate. Moreover, a newly-developed method for lifetime evaluation based on the Weibul distribution shows the benefits of using core gating patterns. E.g., the new Youngest-First Round-Robin (YFRR) pattern enables up to 31% increase in system's lifetime compared to a simple Round-Robin.
During the last years, the asynchronous design style has been rediscovered as a potential solution to upcoming design issues in deep-submicron technologies. However, besides the lack of commercial tools supporting this design style, one major challenge is the test of asynchronous designs. Especially their event-driven behavior leads to problems during test. Basically, the timing of asynchronous circuits is determined by gate and wire delays that are sensitive to variations of environmental parameters (process, voltage and temperature). This leads to uncertainties in the timing of the responses. Consequently, standard commercial test systems cannot be used, because such systems read the responses at specific cycles and, therefore, could reject fault-free devices. Furthermore, available hardware testers are, in principle, not designed to react to signal events from the design-under-test as it is necessary to establish asynchronous communication via handshake signalling. As a result, even simple functional tests that only apply stimuli and read the responses of the design-under-test cannot be realized without preparatory measures. This work addresses these issues and proposes a concept to enable functional tests of asynchronous designs. The concept is based on a special test processor that provides generic interfaces used to establish asynchronous handshake communication with a device-under-test. By this, elastic functional tests can be realized that overcome the static timing of conventional tests and emulate the real operating environment of the design. Apart from the generic test processor architecture, an essential part of the concept deals with the establishment of the processor as a stand alone or embedded test equipment. A workflow is provided that describes how the device-under-test can be embedded into the test processor environment for performing the tests. Besides the interconnection between the asynchronous design and the test processor, this especially includes the generation of programs that realize the functional tests of the design. A methodology is introduced that generates the desired programs for the processor from a standard functional simulation of the design-under-test. Based on the generic concept, a framework including both a test processor implementation and the realization of the program generation is delivered. In order to evaluate the entire concept, this framework has been applied to functionally test an asynchronous arithmetic-logic-unit. In combination with additional experiments, conducted to determine the required resources, it has been shown that the introduced concept is a suitable approach to test asynchronous designs.
The sensitivity of application-specific integrated circuits (ASICs) to single event effects (SEE) can lead to failures of subsystems which are exposed to increased radiation levels in space and on the ground. The work described in this thesis presents a design methodology for a fully fault-tolerant ASIC that is immune to single event upset effects (SEU) in sequential logic, single event transient effects (SET) in combinatorial logic, and single event latchup effects (SEL). Redundant circuits combined with SEL power switches (SPS) are the basis for a design methodology which achieves this goal. Within the standard ASIC design flow enhancements were made in order to incorporate redundancy and SPS cells and, consequently, enable protection against SEU, SET, and SEL. In order to validate the resulting fault-tolerant circuits a fault-injection environment with carefully designed fault models was developed. The moments of fault occurrence and their durations are modeled according to the real effects in actual hardware. The proposed design methodology was applied to an innovative space craft area network (SCAN) central processor unit, known as middleware switch processor. The measurement results presented in this thesis prove the correct functionality of DMR and SPS circuits, as well as the high fault-tolerance of the implemented ASICs along with moderate overhead with respect to power consumption and occupied silicon area. Irradiation measurements demonstrated the correct design and successful implementation of the SPS cell.