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The thesis addresses the design of monolithically integrated radio frequency amplifiers for X-band applications. The focus is on low-voltage low-noise amplifiers and efficient power amplifiers with high output power level. The challenge here is to realize stable amplifiers with remarkable performance metrics at low supply voltages. The general approach for stabilization amplifiers in the above frequency range is the use of a cascode topology which, however, requests higher supply voltages then single transistor operation. By using a special passive frequency-selective feedback, the use of the cascode topology could be avoided, and the amplifiers are stabilized over the entire frequency spectrum. Simultaneously, this feedback is used to neutralize the intrinsic feedback of the transistor at operating frequencies. As a result, a frequency dependent performance degeneration of the transistor can be mitigated.
This work describes the influence of the passive frequency-selective feedback. Its usage as well its limitation are explained using the examples of a realized low noise amplifier and different power amplifiers. Further, the design of radio frequency amplifiers at X-band frequencies that employs silicon-germanium heterojunction bipolar transistors is described. All amplifiers were either incorporated in a 0.25 µm SiGe:C BiCMOS technology or in a 0.35 µm SiGe:C bipolar technology. The main achievements of this work include:
- A 8.7 GHz narrow-band low noise amplifier incorporated in a 0.35 µm SiGe bipolar technology. The noise figure is 2.2 dB and the gain 28 dB at a supply voltage of 3 V. The low noise amplifier was subsequently used for a design of a double-balanced I/Q mixer.
- Two packaged high efficient power amplifiers operating at a center frequency of 12 GHz. They are incorporated in a 0.35 µm SiGe bipolar technology. One amplifier uses a transformer-based output matching network and achieves 30.9 % of power-added efficiency and 23.9 dBm of maximum output power at a supply voltage of 1.8 V. The second amplifier utilizes an LC-balun for impedance matching at the output and a power-added-efficiency of 38 % at 1.8 V is measured. The maximum output power was 23.4 dBm.
- A power amplifier in a 0.35 µm SiGe bipolar technology that uses power combining techniques to achieve 30 dBm (1 W) and 30 % of power-added efficiency at 10 GHz and 2 V supply voltage.
- Two power amplifiers, incorporated in a 0.25 µm SiGe:C BiCMOS technology, demonstrating the capability of a non-advanced SiGe process to be used for radio frequency power applications. Power combining techniques, the use of the passive frequency-selective feedback and layout optimization enables the realization of power amplifiers which exhibit an output power of 30 dBm and a power-added efficiency of 35 % at supply voltages lower as 2.6 V.
In this work a compact, monolithically integrated, high frequency sigma-delta phase-locked loops (PLLs) designed in 0.13 μm CMOS technology are investigated. The research focuses on the analysis of PLL spurious performance degradation caused by the integrated digital sigma-delta modulator, design and optimization of compact sigma-delta modulators with improved tonal and switching noise performance. The main achievements of this work include: 1. An implementation of MASH (multistage) modulator in the dual edge triggered style is proposed. The implementation offers two advantages over conventional MASH when integrated into the same die with a fractional-N PLL: 1) the modulator’s area is reduced by 15–20%; 2) the switching noise power is distributed in such a manner, that the first reference spur of a synthesizer is not degraded; instead, the glitch energy is shifted to the second multiple of reference frequency; in the work a benefit of such reference spur power distribution is demonstrated. Proposed implementation does not affect logical behavior of the MASH modulator. 2. MASH 1-1-1 (three stages of first order each) sigma-delta modulator with DC dithering used for frequency synthesis applications is investigated. At the expense of minimum additional hardware such dithering topology allows to shift tones to the low frequencies and decrease their power. 3. An oscillator-based dither generator is proposed for the use in MASH 1-1-1 modulator. The generator consumes less current and area, produces much less supply switching noise than a conventional pseudo-random dither generator while keeping modulator’s output free of tones. An empirical study of oscillator-based dither generator is presented. 4. MASH 1-1-1 modulator with direct feedback dithering is investigated. Such dithering topology requires no additional hardware to be implemented. Among the disadvantages of the direct feedback dithering is the addition of small DC offset to the output of MASH modulator and presence of some low power tones in amplitude spectrum. Two fully integrated 11 GHz sigma-delta PLLs incorporating single- and dual edge triggered MASH modulators with different dithering topologies were fabricated in 0.13 μm CMOS process. Spurious, as well as phase noise performance of the PLLs for different modulator topologies was compared. The PLL controlled by the integrated dual edge triggered MASH 1-1-1 modulator exhibited first reference spur below –66 dBc over the whole locking range and fractional spurs power not exceeding –70 dBc within 70% of the division ratio range.
This work demonstrates the design and implementation of a multi-band multi-standard WLAN system consisting of a 5 - 6 GHz receiver and a 24 GHz down-converter. The main challenges are high frequency, broadband, and adaptive operation, power consumption and high integration level. This thesis introduces a multi-standard adaptive receiver concept to fulfill those requirements. The receivers are implemented in a standard 0.13 µm CMOS technology. A direct-conversion architecture for the 5 - 6 GHz band and a heterodyne architecture for a multi-band system are proposed. The most common receiver architectures are analyzed and the wave propagation effects are discussed. Then the most important receiver parameters are derived. Active and passive integrated components are investigated because understanding the device characteristic is a key requirement for a successful high frequency design. Finally, the multi-standard adaptive receiver concept is introduced. The choice of architecture, design and implementation of each of the receiver building blocks are discussed. The functionality of the 5 - 6 GHz receiver and the 24 GHz down-converter is demonstrated by the performance measurements. The main achievements of this work include: Firstly, a 5-6 GHz LNA integrated in 0.13 µm CMOS technology. The amplifier exhibits a gain of 16.5 dB, noise figure of 2.9 dB and 1 dB input compression point of -6.5dBm at power consumption of 7.5mW. The circuit features robust built-in input ESD protection. Secondly, a 5-6 GHz zero-IF receiver with analog pre-processing features a noise figure of 3.8 dB at the conversion gain of 43.4 dB. The channel select filter corner frequency is tunable to 6.5, 10, 20 and 50 MHz. The implemented analog pre-processing loop allows to adopt the linearity of the receiver to the input signal level. Thirdly, a 23-24 GHz tuned down-converter achieved the gain of 21.8 dB, noise figure of 6.8 dB and 1 dB input compression point of -16.7dBm at power consumption of 58.5mW.
This thesis presents the design and implementation of the RF power amplifiers in modern silicon based technologies. The main challenge is to include power amplifier on a single chip with output power level in watts, operating at high frequencies where the transit frequency (fT) is just a few times higher than the operating frequency. This work describes the design procedure for bipolar and CMOS transformer-based Class-A, Class-AB and Class-B power amplifiers. The design procedure is based on the HICUM for bipolar and BSIM4 for CMOS transistor models and is divided in four parts: •Building a one transistor prototype power amplifier which is based on the analytical analysis of the output characteristics and transistor model. •Load-pull simulation to define the final input and output impedances. •Derivation of the analytical equations for the transformer-based matching network. •Design of the final transformer-based push-pull power amplifier. A good agreement between the proposed analytical analysis and large-signal (harmonic balance) simulation results proofs usefulness of the proposed power amplifier design approach. Additionally, it shows the contribution of the separated devices at the final design that helps to find a technology limits in the current circuit design. The main achievements include: •A 2.4 GHz power amplifier in 0.13 um CMOS technology. An output power of 28 dBm is achieved with a power added efficiency of 48 % at a supply voltage of 1.2 V [Vasylyev 04]. •Two 17 GHz power amplifiers in 0.13 um CMOS technology (one fully integrated while the other with external matching network) with output power exceeding 50 mW. The former exhibits a power added efficiency of 9.3 % while the latter a 15.6 % power added efficiency [Vasylyev 06]. •A fully integrated K and Ka bands power amplifier in 0.13 um CMOS technology. A 13 dBm output power along with power added efficiency of 13 % is achieved at an operating frequency of 25.7 GHz with 1.2 V supply [Vasylyev 05,a]. •A fully integrated power amplifier based on a novel power combining transformer structure in 28 GHz-fT SiGe-bipolar technology. A 32 dBm output power along with power added efficiency of 30 % is achieved at an operating frequency of 2.12 GHz with 3.5 V supply [Vasylyev 05,b].